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From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH for-9.0 v11 03/18] target/riscv/tcg: update priv_ver on user_set extensions
Date: Fri, 24 Nov 2023 10:23:57 +0100	[thread overview]
Message-ID: <20231124-92b499e54aa4a447386fac16@orel> (raw)
In-Reply-To: <20231123185122.1100436-4-dbarboza@ventanamicro.com>

On Thu, Nov 23, 2023 at 03:51:07PM -0300, Daniel Henrique Barboza wrote:
> We'll add a new bare CPU type that won't have any default priv_ver. This
> means that the CPU will default to priv_ver = 0, i.e. 1.10.0.
> 
> At the same we'll allow these CPUs to enable extensions at will, but
> then, if the extension has a priv_ver newer than 1.10, we'll end up
> disabling it. Users will then need to manually set priv_ver to something
> other than 1.10 to enable the extensions they want, which is not ideal.
> 
> Change the setter() of extensions to allow user enabled extensions to
> bump the priv_ver of the CPU. This will make it convenient for users to
> enable extensions for CPUs that doesn't set a default priv_ver.
> 
> This change does not affect any existing CPU: vendor CPUs does not allow
> extensions to be enabled, and generic CPUs are already set to priv_ver
> LATEST.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
>  target/riscv/tcg/tcg-cpu.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)
> 
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 7670120673..d279314624 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -114,6 +114,26 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)
>      g_assert_not_reached();
>  }
>  
> +static void cpu_validate_multi_ext_priv_ver(CPURISCVState *env,
> +                                            uint32_t ext_offset)

We should probably name this cpu_bump_multi_ext_priv_ver(). "validate"
implies we're checking something and either returning an error when it's
not what we expect or asserting on unexpected input. We do neither here,
we just bump priv_ver, when necessary.

Thanks,
drew


  reply	other threads:[~2023-11-24  9:25 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-23 18:51 [PATCH for-9.0 v11 00/18] rv64i and rva22u64 CPUs, RVA22U64 profile support Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 01/18] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 02/18] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 03/18] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2023-11-24  9:23   ` Andrew Jones [this message]
2023-11-24 11:55     ` Daniel Henrique Barboza
2023-11-24 13:49       ` Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 04/18] target/riscv: add rv64i CPU Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 05/18] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 06/18] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 07/18] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 08/18] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 09/18] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 10/18] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2023-11-24  9:26   ` Andrew Jones
2023-11-23 18:51 ` [PATCH for-9.0 v11 11/18] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 12/18] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 13/18] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 14/18] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 15/18] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 16/18] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 17/18] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2023-11-23 18:51 ` [PATCH for-9.0 v11 18/18] target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza

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