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[46.135.91.180]) by smtp.gmail.com with ESMTPSA id h4-20020adfa4c4000000b0032d8eecf901sm3922481wrb.3.2023.11.24.01.57.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 01:57:34 -0800 (PST) Date: Fri, 24 Nov 2023 10:57:33 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH for-9.0 2/7] target/riscv: add priv ver restriction to profiles Message-ID: <20231124-9f593580898dcebbdb590bff@orel> References: <20231123191532.1101644-1-dbarboza@ventanamicro.com> <20231123191532.1101644-3-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231123191532.1101644-3-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Nov 23, 2023 at 04:15:27PM -0300, Daniel Henrique Barboza wrote: > Some profiles, like RVA22S64, has a priv_spec requirement. > > Make this requirement explicit for all profiles. We'll validate this > requirement finalize() time and, in case the user chooses an > incompatible priv_spec while activating a profile, a warning will be > shown. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 2 ++ > target/riscv/tcg/tcg-cpu.c | 30 ++++++++++++++++++++++++++++++ > 3 files changed, 33 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 59b131c1fc..29a9f77702 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1537,6 +1537,7 @@ Property riscv_cpu_options[] = { > static RISCVCPUProfile RVA22U64 = { > .name = "rva22u64", > .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU, > + .priv_spec = RISCV_PROFILE_ATTR_UNUSED, > .ext_offsets = { > CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause), > CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5ff629650d..1f34eda1e4 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -81,10 +81,12 @@ typedef struct riscv_cpu_profile { > uint32_t misa_ext; > bool enabled; > bool user_set; > + int priv_spec; > const int32_t ext_offsets[]; > } RISCVCPUProfile; > > #define RISCV_PROFILE_EXT_LIST_END -1 > +#define RISCV_PROFILE_ATTR_UNUSED -1 > > extern RISCVCPUProfile *riscv_profiles[]; > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index ddf37b25f3..a26cc6f093 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -74,6 +74,20 @@ static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit, > } > } > > +static const char *cpu_priv_ver_to_str(int priv_ver) > +{ > + switch (priv_ver) { > + case PRIV_VERSION_1_10_0: > + return "v1.10.0"; > + case PRIV_VERSION_1_11_0: > + return "v1.11.0"; > + case PRIV_VERSION_1_12_0: > + return "v1.12.0"; > + } > + > + g_assert_not_reached(); > +} > + > static void riscv_cpu_synchronize_from_tb(CPUState *cs, > const TranslationBlock *tb) > { > @@ -764,11 +778,23 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > static void riscv_cpu_validate_profile(RISCVCPU *cpu, > RISCVCPUProfile *profile) > { > + CPURISCVState *env = &cpu->env; > const char *warn_msg = "Profile %s mandates disabled extension %s"; > bool send_warn = profile->user_set && profile->enabled; > bool profile_impl = true; > int i; > > + if (profile->priv_spec != env->priv_ver) { Shouldn't this be something like if (profile->priv_spec != RISCV_PROFILE_ATTR_UNUSED && profile->priv_spec != env->priv_ver) > + profile_impl = false; > + > + if (send_warn) { > + warn_report("Profile %s requires priv spec %s, " > + "but priv ver %s was set", profile->name, > + cpu_priv_ver_to_str(profile->priv_spec), > + cpu_priv_ver_to_str(env->priv_ver)); > + } > + } > + > for (i = 0; misa_bits[i] != 0; i++) { > uint32_t bit = misa_bits[i]; > > @@ -1057,6 +1083,10 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name, > profile->user_set = true; > profile->enabled = value; > > + if (profile->enabled) { > + cpu->env.priv_ver = profile->priv_spec; > + } > + > for (i = 0; misa_bits[i] != 0; i++) { > uint32_t bit = misa_bits[i]; > > -- > 2.41.0 > Thanks, drew