qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
	alistair.francis@wdc.com,  bmeng@tinylab.org,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	 palmer@rivosinc.com
Subject: Re: [PATCH for-9.0 7/7] target/riscv: add rva22s64 cpu
Date: Fri, 24 Nov 2023 18:16:44 +0100	[thread overview]
Message-ID: <20231124-c0d3f3a3d9ea69501ba2a1aa@orel> (raw)
In-Reply-To: <20231123191532.1101644-8-dbarboza@ventanamicro.com>

On Thu, Nov 23, 2023 at 04:15:32PM -0300, Daniel Henrique Barboza wrote:
> Add a new profile CPU 'rva22s64' to work as an alias of
> 
> -cpu rv64i,rva22s64
> 
> Like the existing rva22u64 CPU already does with the RVA22U64 profile.
> 
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>  target/riscv/cpu-qom.h | 1 +
>  target/riscv/cpu.c     | 8 ++++++++
>  2 files changed, 9 insertions(+)
> 
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 12fe78fc52..9219c2fcc3 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -36,6 +36,7 @@
>  #define TYPE_RISCV_CPU_BASE128          RISCV_CPU_TYPE_NAME("x-rv128")
>  #define TYPE_RISCV_CPU_RV64I            RISCV_CPU_TYPE_NAME("rv64i")
>  #define TYPE_RISCV_CPU_RVA22U64         RISCV_CPU_TYPE_NAME("rva22u64")
> +#define TYPE_RISCV_CPU_RVA22S64         RISCV_CPU_TYPE_NAME("rva22s64")
>  #define TYPE_RISCV_CPU_IBEX             RISCV_CPU_TYPE_NAME("lowrisc-ibex")
>  #define TYPE_RISCV_CPU_SHAKTI_C         RISCV_CPU_TYPE_NAME("shakti-c")
>  #define TYPE_RISCV_CPU_SIFIVE_E31       RISCV_CPU_TYPE_NAME("sifive-e31")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index d00548d164..f6d1d4c7a6 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1631,6 +1631,13 @@ static void rva22u64_profile_cpu_init(Object *obj)
>  
>      RVA22U64.enabled = true;
>  }
> +
> +static void rva22s64_profile_cpu_init(Object *obj)
> +{
> +    rv64i_bare_cpu_init(obj);
> +
> +    RVA22S64.enabled = true;
> +}
>  #endif
>  
>  static const gchar *riscv_gdb_arch_name(CPUState *cs)
> @@ -1975,6 +1982,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
>      DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,  rv128_base_cpu_init),
>      DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
>      DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
> +    DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
>  #endif
>  };
>  
> -- 
> 2.41.0
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>


      reply	other threads:[~2023-11-24 17:17 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-23 19:15 [PATCH for-9.0 0/7] target/riscv: implement RVA22S64 profile Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 1/7] target/riscv: implement svade Daniel Henrique Barboza
2023-11-24  9:52   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 2/7] target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza
2023-11-24  9:57   ` Andrew Jones
2023-11-24 11:42     ` Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 3/7] target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza
2023-11-24 17:06   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 4/7] target/riscv/cpu: add riscv_cpu_is_32bit() Daniel Henrique Barboza
2023-11-24 17:17   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 5/7] target/riscv: add satp_mode profile support Daniel Henrique Barboza
2023-11-24 17:09   ` Andrew Jones
2023-11-23 19:15 ` [PATCH for-9.0 6/7] target/riscv: add RVA22S64 profile Daniel Henrique Barboza
2023-11-24 17:16   ` Andrew Jones
2023-11-24 20:13     ` Daniel Henrique Barboza
2023-11-23 19:15 ` [PATCH for-9.0 7/7] target/riscv: add rva22s64 cpu Daniel Henrique Barboza
2023-11-24 17:16   ` Andrew Jones [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20231124-c0d3f3a3d9ea69501ba2a1aa@orel \
    --to=ajones@ventanamicro.com \
    --cc=alistair.francis@wdc.com \
    --cc=bmeng@tinylab.org \
    --cc=dbarboza@ventanamicro.com \
    --cc=liwei1518@gmail.com \
    --cc=palmer@rivosinc.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).