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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	qemu-devel@nongnu.org
Subject: [PATCH v2 1/7] target/ppc: Rename TBL to TB on 64-bit
Date: Fri, 24 Nov 2023 16:39:55 +1000	[thread overview]
Message-ID: <20231124064001.198572-2-npiggin@gmail.com> (raw)
In-Reply-To: <20231124064001.198572-1-npiggin@gmail.com>

From the earliest PowerPC ISA, TBR (later SPR) 268 has been called TB
and accessed with mftb instruction. The problem is that TB is the name
of the 64-bit register, and 32-bit implementations can only read the
lower half with one instruction, so 268 has also been called TBL and
it does only read TBL on 32-bit.

Change SPR 268 to be called TB on 64-bit implementations.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/ppc/helper_regs.c  | 4 ++++
 target/ppc/ppc-qmp-cmds.c | 4 ++++
 2 files changed, 8 insertions(+)

diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index f380342d4d..8c00ed8c06 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -460,7 +460,11 @@ void register_generic_sprs(PowerPCCPU *cpu)
     }
 
     /* Time base */
+#if defined(TARGET_PPC64)
+    spr_register(env, SPR_VTBL,  "TB",
+#else
     spr_register(env, SPR_VTBL,  "TBL",
+#endif
                  &spr_read_tbl, SPR_NOACCESS,
                  &spr_read_tbl, SPR_NOACCESS,
                  0x00000000);
diff --git a/target/ppc/ppc-qmp-cmds.c b/target/ppc/ppc-qmp-cmds.c
index f9acc21056..ffaff59e78 100644
--- a/target/ppc/ppc-qmp-cmds.c
+++ b/target/ppc/ppc-qmp-cmds.c
@@ -103,7 +103,11 @@ const MonitorDef monitor_defs[] = {
     { "xer", 0, &monitor_get_xer },
     { "msr", offsetof(CPUPPCState, msr) },
     { "tbu", 0, &monitor_get_tbu, },
+#if defined(TARGET_PPC64)
+    { "tb", 0, &monitor_get_tbl, },
+#else
     { "tbl", 0, &monitor_get_tbl, },
+#endif
     { NULL },
 };
 
-- 
2.42.0



  reply	other threads:[~2023-11-24  6:42 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-24  6:39 [PATCH v2 0/7] ppc: pnv ChipTOD and various timebase fixes Nicholas Piggin
2023-11-24  6:39 ` Nicholas Piggin [this message]
2023-11-24  7:11   ` [PATCH v2 1/7] target/ppc: Rename TBL to TB on 64-bit Cédric Le Goater
2023-11-24  6:39 ` [PATCH v2 2/7] target/ppc: Improve timebase register defines naming Nicholas Piggin
2023-11-24  7:12   ` Cédric Le Goater
2023-11-24  6:39 ` [PATCH v2 3/7] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2023-11-24  7:12   ` Cédric Le Goater
2023-11-24  6:39 ` [PATCH v2 4/7] pnv/chiptod: Add POWER9/10 chiptod model Nicholas Piggin
2023-11-24  6:46   ` Nicholas Piggin
2023-11-24  7:12   ` Cédric Le Goater
2023-11-24  7:16   ` Cédric Le Goater
2023-11-24 11:40     ` Nicholas Piggin
2023-11-24 12:10       ` Cédric Le Goater
2023-11-24  6:39 ` [PATCH v2 5/7] pnv/chiptod: Implement the ChipTOD to Core transfer Nicholas Piggin
2023-11-24  7:18   ` Cédric Le Goater
2023-11-24 12:52   ` Cédric Le Goater
2023-11-24  6:40 ` [PATCH v2 6/7] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2023-11-24  6:40 ` [PATCH v2 7/7] target/ppc: Add SMT support to time facilities Nicholas Piggin

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