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Fri, 24 Nov 2023 09:22:34 -0800 (PST) Received: from imammedo.users.ipa.redhat.com ([185.140.112.229]) by smtp.gmail.com with ESMTPSA id v20-20020a05620a441400b0077d63e97725sm1370129qkp.95.2023.11.24.09.22.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 24 Nov 2023 09:22:34 -0800 (PST) Date: Fri, 24 Nov 2023 18:22:29 +0100 From: Igor Mammedov To: Salil Mehta Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH V7 0/8] Add architecture agnostic code to support vCPU Hotplug Message-ID: <20231124182229.34dd52cf@imammedo.users.ipa.redhat.com> In-Reply-To: <20231113201236.30668-1-salil.mehta@huawei.com> References: <20231113201236.30668-1-salil.mehta@huawei.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 13 Nov 2023 20:12:28 +0000 Salil Mehta wrote: > Virtual CPU hotplug support is being added across various architectures[1][3]. > This series adds various code bits common across all architectures: > > 1. vCPU creation and Parking code refactor [Patch 1] > 2. Update ACPI GED framework to support vCPU Hotplug [Patch 2,3] > 3. ACPI CPUs AML code change [Patch 4,5] > 4. Helper functions to support unrealization of CPU objects [Patch 6,7] > 5. Docs [Patch 8] [...] forgot to mention, you probably need to add to series migration code as well as it should be the same for both targets. (mostly copy-paste from q35 or piix4 and making sure it doesn't break old qemu (aka not enabled/sent over wire if cpu hotplug event is disabled))