From: Hyeonggon Yoo <42.hyeyoo@gmail.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
Fan Ni <fan.ni@samsung.com>,
"Michael S . Tsirkin" <mst@redhat.com>
Cc: linux-cxl@lore.kernel.org, qemu-devel@nongnu.org,
Davidlohr Bueso <dave@stgolabs.net>,
Hyeonggon Yoo <42.hyeyoo@gmail.com>
Subject: [PATCH v1 1/2] hw/cxl/device: read from register values in mdev_reg_read()
Date: Mon, 27 Nov 2023 19:58:29 +0900 [thread overview]
Message-ID: <20231127105830.2104954-2-42.hyeyoo@gmail.com> (raw)
In-Reply-To: <20231127105830.2104954-1-42.hyeyoo@gmail.com>
In the current mdev_reg_read() implementation, it consistently returns
that the Media Status is Ready (01b). This was fine until commit
25a52959f99d ("hw/cxl: Add support for device sanitation") because the
media was presumed to be ready.
However, as per the CXL 3.0 spec "8.2.9.8.5.1 Sanitize (Opcode 4400h)",
during sanitation, the Media State should be set to Disabled (11b). The
mentioned commit correctly sets it to Disabled, but mdev_reg_read()
still returns Media Status as Ready.
To address this, update mdev_reg_read() to read register values instead
of returning dummy values.
Fixes: commit 25a52959f99d ("hw/cxl: Add support for device sanitation")
Signed-off-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
---
hw/cxl/cxl-device-utils.c | 17 +++++++++++------
include/hw/cxl/cxl_device.h | 4 +++-
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/hw/cxl/cxl-device-utils.c b/hw/cxl/cxl-device-utils.c
index 61a3c4dc2e..f1111eb20f 100644
--- a/hw/cxl/cxl-device-utils.c
+++ b/hw/cxl/cxl-device-utils.c
@@ -229,12 +229,9 @@ static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
{
- uint64_t retval = 0;
-
- retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
- retval = FIELD_DP64(retval, CXL_MEM_DEV_STS, MBOX_READY, 1);
+ CXLDeviceState *cxl_dstate = opaque;
- return retval;
+ return cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];
}
static void ro_reg_write(void *opaque, hwaddr offset, uint64_t value,
@@ -371,7 +368,15 @@ static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
cxl_dstate->mbox_msi_n = msi_n;
}
-static void memdev_reg_init_common(CXLDeviceState *cxl_dstate) { }
+static void memdev_reg_init_common(CXLDeviceState *cxl_dstate)
+{
+ uint64_t memdev_status_reg;
+
+ memdev_status_reg = FIELD_DP64(0, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
+ memdev_status_reg = FIELD_DP64(memdev_status_reg, CXL_MEM_DEV_STS,
+ MBOX_READY, 1);
+ cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS] = memdev_status_reg;
+}
void cxl_device_register_init_t3(CXLType3Dev *ct3d)
{
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index befb5f884b..873e6d6ab1 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -353,7 +353,9 @@ static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val)
{
uint64_t dev_status_reg;
- dev_status_reg = FIELD_DP64(0, CXL_MEM_DEV_STS, MEDIA_STATUS, val);
+ dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS];
+ dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS,
+ val);
cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS] = dev_status_reg;
}
#define cxl_dev_disable_media(cxlds) \
--
2.39.1
next prev parent reply other threads:[~2023-11-27 10:59 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-27 10:58 [PATCH v1 0/2] A Fixup for "QEMU: CXL mailbox rework and features (Part 1)" Hyeonggon Yoo
2023-11-27 10:58 ` Hyeonggon Yoo [this message]
2023-11-27 20:27 ` [PATCH v1 1/2] hw/cxl/device: read from register values in mdev_reg_read() Davidlohr Bueso
2023-11-28 0:42 ` Hyeonggon Yoo
2023-11-28 5:42 ` Davidlohr Bueso
2023-11-30 16:32 ` Jonathan Cameron via
2023-12-04 3:38 ` Davidlohr Bueso
2023-11-27 10:58 ` [PATCH v1 2/2] hw/mem/cxl_type3: allocate more vectors for MSI-X Hyeonggon Yoo
2023-11-27 17:53 ` Davidlohr Bueso
2023-11-28 0:27 ` Hyeonggon Yoo
2023-11-28 12:46 ` Jonathan Cameron via
2023-11-30 5:53 ` Hyeonggon Yoo
2023-11-28 7:31 ` [PATCH v1 0/2] A Fixup for "QEMU: CXL mailbox rework and features (Part 1)" Michael S. Tsirkin
2023-11-29 7:40 ` Hyeonggon Yoo
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