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From: Hyeonggon Yoo <42.hyeyoo@gmail.com>
To: Jonathan Cameron <jonathan.cameron@huawei.com>,
	Fan Ni <fan.ni@samsung.com>,
	"Michael S . Tsirkin" <mst@redhat.com>
Cc: linux-cxl@lore.kernel.org, qemu-devel@nongnu.org,
	Davidlohr Bueso <dave@stgolabs.net>,
	Hyeonggon Yoo <42.hyeyoo@gmail.com>
Subject: [PATCH v1 2/2] hw/mem/cxl_type3: allocate more vectors for MSI-X
Date: Mon, 27 Nov 2023 19:58:30 +0900	[thread overview]
Message-ID: <20231127105830.2104954-3-42.hyeyoo@gmail.com> (raw)
In-Reply-To: <20231127105830.2104954-1-42.hyeyoo@gmail.com>

commit 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background
completion") enables notifying background command completion via MSI-X
interrupt (vector number 9).

However, the commit uses vector number 9 but the maximum number of
entries is less thus resulting in error below. Fix it by passing
nentries = 10 when calling msix_init_exclusive_bar().

 # echo 1 > sanitize
 Background command 4400h finished: success
 qemu-system-x86_64: ../hw/pci/msix.c:529: msix_notify: Assertion `vector < dev->msix_entries_nr' failed.

Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background completion")
Signed-off-by: Hyeonggon Yoo <42.hyeyoo@gmail.com>
---
 hw/mem/cxl_type3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 52647b4ac7..72d9371347 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -685,7 +685,7 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp)
     ComponentRegisters *regs = &cxl_cstate->crb;
     MemoryRegion *mr = &regs->component_registers;
     uint8_t *pci_conf = pci_dev->config;
-    unsigned short msix_num = 6;
+    unsigned short msix_num = 10;
     int i, rc;
 
     QTAILQ_INIT(&ct3d->error_list);
-- 
2.39.1



  parent reply	other threads:[~2023-11-27 10:59 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-27 10:58 [PATCH v1 0/2] A Fixup for "QEMU: CXL mailbox rework and features (Part 1)" Hyeonggon Yoo
2023-11-27 10:58 ` [PATCH v1 1/2] hw/cxl/device: read from register values in mdev_reg_read() Hyeonggon Yoo
2023-11-27 20:27   ` Davidlohr Bueso
2023-11-28  0:42     ` Hyeonggon Yoo
2023-11-28  5:42       ` Davidlohr Bueso
2023-11-30 16:32     ` Jonathan Cameron via
2023-12-04  3:38       ` Davidlohr Bueso
2023-11-27 10:58 ` Hyeonggon Yoo [this message]
2023-11-27 17:53   ` [PATCH v1 2/2] hw/mem/cxl_type3: allocate more vectors for MSI-X Davidlohr Bueso
2023-11-28  0:27     ` Hyeonggon Yoo
2023-11-28 12:46       ` Jonathan Cameron via
2023-11-30  5:53         ` Hyeonggon Yoo
2023-11-28  7:31 ` [PATCH v1 0/2] A Fixup for "QEMU: CXL mailbox rework and features (Part 1)" Michael S. Tsirkin
2023-11-29  7:40   ` Hyeonggon Yoo

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