[PATCH 0/2] Make vector whole-register move (vmv) depend on vtype register

[PATCH 0/2] Make vector whole-register move (vmv) depend on vtype register

[Max Chou]

The ratified v1.0 version of RISC-V V spec section 16.6 says that 
`The instructions operate as if EEW=SEW.`.

So the whole vector register move instructions depend on the vtype
register that means the implementation needs to be fixed to raise an
illegal-instruction exception when vtype.vill=1, as is the case with
most other vector instructions.

Reference:
- https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#whole-vector-register-move
- https://github.com/riscv/riscv-v-spec/commit/856fe5bd1cb135c39258e6ca941bf234ae63e1b1

Max Chou (2):
  target/riscv: Add vill check for whole vector register move
    instructions
  target/riscv: The whole vector register move instructions depend on
    vsew

 target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

-- 
2.34.1

[PATCH 1/2] target/riscv: Add vill check for whole vector register move instructions

[Max Chou]

The ratified version of RISC-V V spec section 16.6 says that
`The instructions operate as if EEW=SEW`.

So the whole vector register move instructions depend on the vtype
register that means the whole vector register move instructions should
raise an illegal-instruction exception when vtype.vill=1.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 78bd363310d..114ad87397f 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3631,13 +3631,14 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
 }
 
 /*
- * Whole Vector Register Move Instructions ignore vtype and vl setting.
- * Thus, we don't need to check vill bit. (Section 16.6)
+ * Whole Vector Register Move Instructions depend on vtype register(vsew).
+ * Thus, we need to check vill bit. (Section 16.6)
  */
 #define GEN_VMV_WHOLE_TRANS(NAME, LEN)                             \
 static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
 {                                                                       \
     if (require_rvv(s) &&                                               \
+        vext_check_isa_ill(s) &&                                        \
         QEMU_IS_ALIGNED(a->rd, LEN) &&                                  \
         QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
         uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
-- 
2.34.1

[PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew

[Max Chou]

The RISC-V v spec 16.6 section says that the whole vector register move
instructions operate as if EEW=SEW. So it should depends on the vsew
field of vtype register.

Signed-off-by: Max Chou <max.chou@sifive.com>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 114ad87397f..3871f0ea73d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
         QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
         uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
         if (s->vstart_eq_zero) {                                        \
-            /* EEW = 8 */                                               \
-            tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),                  \
+            tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),                \
                              vreg_ofs(s, a->rs2), maxsz, maxsz);        \
             mark_vs_dirty(s);                                           \
         } else {                                                        \
-- 
2.34.1

Re: [PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew

[Richard Henderson]

On 11/29/23 11:03, Max Chou wrote:
> The RISC-V v spec 16.6 section says that the whole vector register move
> instructions operate as if EEW=SEW. So it should depends on the vsew
> field of vtype register.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 114ad87397f..3871f0ea73d 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
>           QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
>           uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \
>           if (s->vstart_eq_zero) {                                        \
> -            /* EEW = 8 */                                               \
> -            tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd),                  \
> +            tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),                \
>                                vreg_ofs(s, a->rs2), maxsz, maxsz);        \
>               mark_vs_dirty(s);                                           \
>           } else {                                                        \

This perhaps makes things clearer in the translator, but there is no difference in the tcg 
code generation end.  All logic operations (and, or, xor, mov...) ignore the element size.

Acked-by: Richard Henderson <richard.henderson@linaro.org>


r~

Re: [PATCH 1/2] target/riscv: Add vill check for whole vector register move instructions

[Daniel Henrique Barboza]

On 11/29/23 14:03, Max Chou wrote:
> The ratified version of RISC-V V spec section 16.6 says that
> `The instructions operate as if EEW=SEW`.
> 
> So the whole vector register move instructions depend on the vtype
> register that means the whole vector register move instructions should
> raise an illegal-instruction exception when vtype.vill=1.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 78bd363310d..114ad87397f 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3631,13 +3631,14 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
>   }
>   
>   /*
> - * Whole Vector Register Move Instructions ignore vtype and vl setting.
> - * Thus, we don't need to check vill bit. (Section 16.6)
> + * Whole Vector Register Move Instructions depend on vtype register(vsew).
> + * Thus, we need to check vill bit. (Section 16.6)
>    */
>   #define GEN_VMV_WHOLE_TRANS(NAME, LEN)                             \
>   static bool trans_##NAME(DisasContext *s, arg_##NAME * a)               \
>   {                                                                       \
>       if (require_rvv(s) &&                                               \
> +        vext_check_isa_ill(s) &&                                        \
>           QEMU_IS_ALIGNED(a->rd, LEN) &&                                  \
>           QEMU_IS_ALIGNED(a->rs2, LEN)) {                                 \
>           uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN;                 \

Re: [PATCH 0/2] Make vector whole-register move (vmv) depend on vtype register

[Alistair Francis]

On Thu, Nov 30, 2023 at 3:05 AM Max Chou <max.chou@sifive.com> wrote:
>
> The ratified v1.0 version of RISC-V V spec section 16.6 says that
> `The instructions operate as if EEW=SEW.`.
>
> So the whole vector register move instructions depend on the vtype
> register that means the implementation needs to be fixed to raise an
> illegal-instruction exception when vtype.vill=1, as is the case with
> most other vector instructions.
>
> Reference:
> - https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#whole-vector-register-move
> - https://github.com/riscv/riscv-v-spec/commit/856fe5bd1cb135c39258e6ca941bf234ae63e1b1
>
> Max Chou (2):
>   target/riscv: Add vill check for whole vector register move
>     instructions
>   target/riscv: The whole vector register move instructions depend on
>     vsew

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/insn_trans/trans_rvv.c.inc | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> --
> 2.34.1
>
>