From: Max Chou <max.chou@sifive.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Max Chou <max.chou@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Weiwei Li <liwei1518@gmail.com>,
Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
Richard Henderson <richard.henderson@linaro.org>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>
Subject: [PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew
Date: Thu, 30 Nov 2023 01:03:58 +0800 [thread overview]
Message-ID: <20231129170400.21251-3-max.chou@sifive.com> (raw)
In-Reply-To: <20231129170400.21251-1-max.chou@sifive.com>
The RISC-V v spec 16.6 section says that the whole vector register move
instructions operate as if EEW=SEW. So it should depends on the vsew
field of vtype register.
Signed-off-by: Max Chou <max.chou@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 114ad87397f..3871f0ea73d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3643,8 +3643,7 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
QEMU_IS_ALIGNED(a->rs2, LEN)) { \
uint32_t maxsz = (s->cfg_ptr->vlen >> 3) * LEN; \
if (s->vstart_eq_zero) { \
- /* EEW = 8 */ \
- tcg_gen_gvec_mov(MO_8, vreg_ofs(s, a->rd), \
+ tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd), \
vreg_ofs(s, a->rs2), maxsz, maxsz); \
mark_vs_dirty(s); \
} else { \
--
2.34.1
next prev parent reply other threads:[~2023-11-29 17:24 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-29 17:03 [PATCH 0/2] Make vector whole-register move (vmv) depend on vtype register Max Chou
2023-11-29 17:03 ` [PATCH 1/2] target/riscv: Add vill check for whole vector register move instructions Max Chou
2023-12-04 19:22 ` Daniel Henrique Barboza
2023-11-29 17:03 ` Max Chou [this message]
2023-11-29 17:27 ` [PATCH 2/2] target/riscv: The whole vector register move instructions depend on vsew Richard Henderson
2023-12-06 0:49 ` [PATCH 0/2] Make vector whole-register move (vmv) depend on vtype register Alistair Francis
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