From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
qemu-devel@nongnu.org, "Frédéric Barrat" <fbarrat@linux.ibm.com>
Subject: [PATCH 0/7] ppc: pnv ChipTOD and various timebase fixes
Date: Fri, 1 Dec 2023 22:24:55 +1000 [thread overview]
Message-ID: <20231201122455.143936-2-npiggin@gmail.com> (raw)
In-Reply-To: <20231201122455.143936-1-npiggin@gmail.com>
The chiptod/TFMR/state machine is not really tied to the other
time register fixes, but they touch some of the same code, and
logically same facility.
Changes since v1 of chiptod patches:
- Split hackish ChipTOD<->TFMR/TBST interface into its own patch
- Fix multi-socket addressing on P9 / chip ID mode (P10 works)
- Change chiptod primary/secondary setting to use class properties
- Add more comments to explain TOD overview and timebase state
machine.
- SMT support for TFMR, some functionality is limited to thread 0.
- FIRMWARE_CONTROL_ERROR bit implemented in TFMR.
- Misc cleanups and bug fixes.
The hacky part, addressing core from chiptod, is still hacky. Is
there strong objection to it?
This successfully runs skiboot chiptod initialisation code with
POWER9 and POWER10 multi-socket, multi-core, SMT. That requires
skiboot 7.1 (not in-tree), otherwise chiptod init is skipped on
QEMU machines.
Thanks,
Nick
Nicholas Piggin (7):
target/ppc: Rename TBL to TB on 64-bit
target/ppc: Improve timebase register defines naming
target/ppc: Fix move-to timebase SPR access permissions
pnv/chiptod: Add POWER9/10 chiptod model
pnv/chiptod: Implement the ChipTOD to Core transfer
target/ppc: Implement core timebase state machine and TFMR
target/ppc: Add SMT support to time facilities
include/hw/ppc/pnv_chip.h | 3 +
include/hw/ppc/pnv_chiptod.h | 55 ++++
include/hw/ppc/pnv_core.h | 4 +
include/hw/ppc/pnv_xscom.h | 9 +
target/ppc/cpu.h | 50 +++-
hw/ppc/pnv.c | 63 +++++
hw/ppc/pnv_chiptod.c | 509 +++++++++++++++++++++++++++++++++++
target/ppc/helper_regs.c | 39 ++-
target/ppc/ppc-qmp-cmds.c | 4 +
target/ppc/timebase_helper.c | 309 ++++++++++++++++++++-
target/ppc/translate.c | 42 ++-
hw/ppc/meson.build | 1 +
hw/ppc/trace-events | 4 +
13 files changed, 1067 insertions(+), 25 deletions(-)
create mode 100644 include/hw/ppc/pnv_chiptod.h
create mode 100644 hw/ppc/pnv_chiptod.c
--
2.42.0
next prev parent reply other threads:[~2023-12-01 12:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 12:24 [PATCH] target/ppc: Re-name registers to match ISA Nicholas Piggin
2023-12-01 12:24 ` Nicholas Piggin [this message]
2024-01-23 7:34 ` Cédric Le Goater
-- strict thread matches above, loose matches on Subject: below --
2023-11-23 10:30 [PATCH 0/7] ppc: pnv ChipTOD and various timebase fixes Nicholas Piggin
2023-11-23 17:09 ` Cédric Le Goater
2023-11-24 6:02 ` Nicholas Piggin
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