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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv Date: Tue, 12 Dec 2023 17:29:00 +0100 Message-ID: <20231212162935.42910-1-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, When a MPCore cluster is used, the Cortex-A cores belong the the cluster container, not to the board/soc layer. This series move the creation of vCPUs to the MPCore private container. Doing so we consolidate the QOM model, moving common code in a central place (abstract MPCore parent). This eventually allow removing one qemu_get_cpu() use, which we want to remove in heterogeneous machines (machines using MPCore are candidate for heterogeneous emulation). Maybe these hw/cpu/arm/ files belong to hw/arm/... Regards, Phil. Philippe Mathieu-Daudé (33): hw/arm/boot: Propagate vCPU to arm_load_dtb() hw/arm/fsl-imx6: Add a local 'gic' variable hw/arm/fsl-imx6ul: Add a local 'gic' variable hw/arm/fsl-imx7: Add a local 'gic' variable hw/cpu: Remove dead Kconfig hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_realize() hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro hw/cpu/arm: Merge {a9mpcore.h, a15mpcore.h} as cortex_mpcore.h hw/cpu/arm: Introduce abstract CORTEX_MPCORE_PRIV QOM type hw/cpu/arm: Have A9MPCORE/A15MPCORE inheritate common CORTEX_MPCORE_PRIV hw/cpu/arm: Create MPCore container in QOM parent hw/cpu/arm: Handle 'num_cores' property once in MPCore parent hw/cpu/arm: Handle 'has_el2/3' properties once in MPCore parent hw/cpu/arm: Handle 'gic-irq' property once in MPCore parent hw/cpu/arm: Handle GIC once in MPCore parent hw/cpu/arm: Document more properties of CORTEX_MPCORE_PRIV QOM type hw/cpu/arm: Replace A15MPPrivState by CortexMPPrivState hw/cpu/arm: Introduce TYPE_A7MPCORE_PRIV for Cortex-A7 MPCore hw/cpu/arm: Consolidate check on max GIC spi supported hw/cpu/arm: Create CPUs once in MPCore parent hw/arm/aspeed_ast2600: Let the A7MPcore create/wire the CPU cores hw/arm/exynos4210: Let the A9MPcore create/wire the CPU cores hw/arm/fsl-imx6: Let the A9MPcore create/wire the CPU cores hw/arm/fsl-imx6ul: Let the A7MPcore create/wire the CPU cores hw/arm/fsl-imx7: Let the A7MPcore create/wire the CPU cores hw/arm/highbank: Let the A9/A15MPcore create/wire the CPU cores hw/arm/vexpress: Let the A9/A15MPcore create/wire the CPU cores hw/arm/xilinx_zynq: Let the A9MPcore create/wire the CPU cores hw/arm/npcm7xx: Let the A9MPcore create/wire the CPU cores hw/cpu/a9mpcore: Remove legacy code hw/cpu/arm: Remove 'num-cpu' property alias hw/cpu/arm: Remove use of qemu_get_cpu() in A7/A15 realize() MAINTAINERS | 3 +- include/hw/arm/aspeed_soc.h | 5 +- include/hw/arm/boot.h | 4 +- include/hw/arm/exynos4210.h | 6 +- include/hw/arm/fsl-imx6.h | 6 +- include/hw/arm/fsl-imx6ul.h | 8 +- include/hw/arm/fsl-imx7.h | 8 +- include/hw/arm/npcm7xx.h | 3 +- include/hw/cpu/a15mpcore.h | 44 ------- include/hw/cpu/a9mpcore.h | 39 ------- include/hw/cpu/cortex_mpcore.h | 135 ++++++++++++++++++++++ hw/arm/aspeed_ast2600.c | 61 ++++------ hw/arm/boot.c | 11 +- hw/arm/exynos4210.c | 60 ++++------ hw/arm/exynos4_boards.c | 6 +- hw/arm/fsl-imx6.c | 84 ++++---------- hw/arm/fsl-imx6ul.c | 65 ++++------- hw/arm/fsl-imx7.c | 103 +++++------------ hw/arm/highbank.c | 56 ++------- hw/arm/mcimx6ul-evk.c | 3 +- hw/arm/mcimx7d-sabre.c | 3 +- hw/arm/npcm7xx.c | 48 ++------ hw/arm/realview.c | 4 +- hw/arm/sabrelite.c | 4 +- hw/arm/vexpress.c | 60 +++------- hw/arm/virt.c | 2 +- hw/arm/xilinx_zynq.c | 30 ++--- hw/cpu/a15mpcore.c | 179 +++++++++++++---------------- hw/cpu/a9mpcore.c | 138 +++++++++------------- hw/cpu/arm11mpcore.c | 23 ++-- hw/cpu/cortex_mpcore.c | 202 +++++++++++++++++++++++++++++++++ hw/cpu/realview_mpcore.c | 30 ++--- hw/arm/Kconfig | 8 +- hw/cpu/Kconfig | 8 -- hw/cpu/meson.build | 1 + 35 files changed, 689 insertions(+), 761 deletions(-) delete mode 100644 include/hw/cpu/a15mpcore.h delete mode 100644 include/hw/cpu/a9mpcore.h create mode 100644 include/hw/cpu/cortex_mpcore.h create mode 100644 hw/cpu/cortex_mpcore.c delete mode 100644 hw/cpu/Kconfig -- 2.41.0