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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/33] hw/cpu/arm: Have A9MPCORE/A15MPCORE inheritate common CORTEX_MPCORE_PRIV Date: Tue, 12 Dec 2023 17:29:11 +0100 Message-ID: <20231212162935.42910-12-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=philmd@linaro.org; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org TYPE_CORTEX_MPCORE_PRIV becomes the common parent to TYPE_A9MPCORE_PRIV and TYPE_A15MPCORE_PRIV. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/cpu/cortex_mpcore.h | 6 ++++-- hw/cpu/a15mpcore.c | 14 ++++++++++++-- hw/cpu/a9mpcore.c | 13 +++++++++++-- hw/arm/Kconfig | 2 ++ 4 files changed, 29 insertions(+), 6 deletions(-) diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h index c5dd7200d0..4084c6003a 100644 --- a/include/hw/cpu/cortex_mpcore.h +++ b/include/hw/cpu/cortex_mpcore.h @@ -32,6 +32,8 @@ OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV) struct CortexMPPrivClass { SysBusDeviceClass parent_class; + + DeviceRealize parent_realize; }; struct CortexMPPrivState { @@ -42,7 +44,7 @@ struct CortexMPPrivState { OBJECT_DECLARE_SIMPLE_TYPE(A9MPPrivState, A9MPCORE_PRIV) struct A9MPPrivState { - SysBusDevice parent_obj; + CortexMPPrivState parent_obj; uint32_t num_cpu; MemoryRegion container; @@ -59,7 +61,7 @@ struct A9MPPrivState { OBJECT_DECLARE_SIMPLE_TYPE(A15MPPrivState, A15MPCORE_PRIV) struct A15MPPrivState { - SysBusDevice parent_obj; + CortexMPPrivState parent_obj; uint32_t num_cpu; uint32_t num_irq; diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 0f56c40b86..5a57145179 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -48,15 +48,23 @@ static void a15mp_priv_initfn(Object *obj) static void a15mp_priv_realize(DeviceState *dev, Error **errp) { + CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); A15MPPrivState *s = A15MPCORE_PRIV(dev); DeviceState *gicdev; SysBusDevice *gicsbd; + Error *local_err = NULL; int i; bool has_el3; bool has_el2 = false; Object *cpuobj; + cc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + gicdev = DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); @@ -158,8 +166,10 @@ static Property a15mp_priv_properties[] = { static void a15mp_priv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass); - dc->realize = a15mp_priv_realize; + device_class_set_parent_realize(dc, a15mp_priv_realize, + &cc->parent_realize); device_class_set_props(dc, a15mp_priv_properties); /* We currently have no saveable state */ } @@ -167,7 +177,7 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data) static const TypeInfo a15mp_types[] = { { .name = TYPE_A15MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_CORTEX_MPCORE_PRIV, .instance_size = sizeof(A15MPPrivState), .instance_init = a15mp_priv_initfn, .class_init = a15mp_priv_class_init, diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index e9cd71e92f..d59e49126b 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -46,11 +46,13 @@ static void a9mp_priv_initfn(Object *obj) static void a9mp_priv_realize(DeviceState *dev, Error **errp) { + CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); A9MPPrivState *s = A9MPCORE_PRIV(dev); DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev; SysBusDevice *scubusdev, *gicbusdev, *gtimerbusdev, *mptimerbusdev, *wdtbusdev; + Error *local_err = NULL; int i; bool has_el3; CPUState *cpu0; @@ -65,6 +67,12 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) return; } + cc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + scudev = DEVICE(&s->scu); qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { @@ -173,15 +181,16 @@ static Property a9mp_priv_properties[] = { static void a9mp_priv_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass); - dc->realize = a9mp_priv_realize; + device_class_set_parent_realize(dc, a9mp_priv_realize, &cc->parent_realize); device_class_set_props(dc, a9mp_priv_properties); } static const TypeInfo a9mp_types[] = { { .name = TYPE_A9MPCORE_PRIV, - .parent = TYPE_SYS_BUS_DEVICE, + .parent = TYPE_CORTEX_MPCORE_PRIV, .instance_size = sizeof(A9MPPrivState), .instance_init = a9mp_priv_initfn, .class_init = a9mp_priv_class_init, diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3040342fcb..ec6e585797 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -648,6 +648,7 @@ config CORTEX_MPCORE config A9MPCORE bool + select CORTEX_MPCORE select A9_GTIMER select A9SCU # snoop control unit select ARM_GIC @@ -655,6 +656,7 @@ config A9MPCORE config A15MPCORE bool + select CORTEX_MPCORE select ARM_GIC config ARM11MPCORE -- 2.41.0