From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
"Tyrone Ting" <kfting@nuvoton.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Manos Pitsidianakis" <manos.pitsidianakis@linaro.org>,
"Eduardo Habkost" <eduardo@habkost.net>,
"Joel Stanley" <joel@jms.id.au>,
"Alistair Francis" <alistair@alistair23.me>,
"Anton Johansson" <anjo@rev.ng>,
"Andrey Smirnov" <andrew.smirnov@gmail.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Hao Wu" <wuhaotsh@google.com>, "Cédric Le Goater" <clg@kaod.org>,
"Jean-Christophe Dubois" <jcd@tribudubois.net>,
"Igor Mitsyanko" <i.mitsyanko@gmail.com>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Andrew Jeffery" <andrew@codeconstruct.com.au>,
"Rob Herring" <robh@kernel.org>,
qemu-arm@nongnu.org,
"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 12/33] hw/cpu/arm: Create MPCore container in QOM parent
Date: Tue, 12 Dec 2023 17:29:12 +0100 [thread overview]
Message-ID: <20231212162935.42910-13-philmd@linaro.org> (raw)
In-Reply-To: <20231212162935.42910-1-philmd@linaro.org>
Move the memory region container creation to the abstract QOM
parent. Children set the region size via the class 'container_size'
field.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
include/hw/cpu/cortex_mpcore.h | 10 ++++++++--
hw/cpu/a15mpcore.c | 17 ++++++++---------
hw/cpu/a9mpcore.c | 18 +++++++++---------
hw/cpu/cortex_mpcore.c | 14 ++++++++++++++
4 files changed, 39 insertions(+), 20 deletions(-)
diff --git a/include/hw/cpu/cortex_mpcore.h b/include/hw/cpu/cortex_mpcore.h
index 4084c6003a..1d94c8769d 100644
--- a/include/hw/cpu/cortex_mpcore.h
+++ b/include/hw/cpu/cortex_mpcore.h
@@ -30,14 +30,22 @@
#define TYPE_CORTEX_MPCORE_PRIV "cortex_mpcore_priv"
OBJECT_DECLARE_TYPE(CortexMPPrivState, CortexMPPrivClass, CORTEX_MPCORE_PRIV)
+/**
+ * CortexMPPrivClass:
+ * @container_size - size of the device's MMIO region
+ */
struct CortexMPPrivClass {
SysBusDeviceClass parent_class;
DeviceRealize parent_realize;
+
+ uint64_t container_size;
};
struct CortexMPPrivState {
SysBusDevice parent_obj;
+
+ MemoryRegion container;
};
#define TYPE_A9MPCORE_PRIV "a9mpcore_priv"
@@ -47,7 +55,6 @@ struct A9MPPrivState {
CortexMPPrivState parent_obj;
uint32_t num_cpu;
- MemoryRegion container;
uint32_t num_irq;
A9SCUState scu;
@@ -65,7 +72,6 @@ struct A15MPPrivState {
uint32_t num_cpu;
uint32_t num_irq;
- MemoryRegion container;
GICState gic;
};
diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index 5a57145179..128941eb50 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -36,12 +36,8 @@ static void a15mp_priv_set_irq(void *opaque, int irq, int level)
static void a15mp_priv_initfn(Object *obj)
{
- SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
A15MPPrivState *s = A15MPCORE_PRIV(obj);
- memory_region_init(&s->container, obj, "a15mp-priv-container", 0x8000);
- sysbus_init_mmio(sbd, &s->container);
-
object_initialize_child(obj, "gic", &s->gic, gic_class_name());
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
}
@@ -51,6 +47,7 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A15MPPrivState *s = A15MPCORE_PRIV(dev);
+ CortexMPPrivState *c = CORTEX_MPCORE_PRIV(dev);
DeviceState *gicdev;
SysBusDevice *gicsbd;
Error *local_err = NULL;
@@ -133,20 +130,20 @@ static void a15mp_priv_realize(DeviceState *dev, Error **errp)
* 0x5600-0x57ff -- GIC virtual interface control for CPU 3
* 0x6000-0x7fff -- GIC virtual CPU interface
*/
- memory_region_add_subregion(&s->container, 0x1000,
+ memory_region_add_subregion(&c->container, 0x1000,
sysbus_mmio_get_region(gicsbd, 0));
- memory_region_add_subregion(&s->container, 0x2000,
+ memory_region_add_subregion(&c->container, 0x2000,
sysbus_mmio_get_region(gicsbd, 1));
if (has_el2) {
- memory_region_add_subregion(&s->container, 0x4000,
+ memory_region_add_subregion(&c->container, 0x4000,
sysbus_mmio_get_region(gicsbd, 2));
- memory_region_add_subregion(&s->container, 0x6000,
+ memory_region_add_subregion(&c->container, 0x6000,
sysbus_mmio_get_region(gicsbd, 3));
for (i = 0; i < s->num_cpu; i++) {
hwaddr base = 0x5000 + i * 0x200;
MemoryRegion *mr = sysbus_mmio_get_region(gicsbd,
4 + s->num_cpu + i);
- memory_region_add_subregion(&s->container, base, mr);
+ memory_region_add_subregion(&c->container, base, mr);
}
}
}
@@ -168,6 +165,8 @@ static void a15mp_priv_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass);
+ cc->container_size = 0x8000;
+
device_class_set_parent_realize(dc, a15mp_priv_realize,
&cc->parent_realize);
device_class_set_props(dc, a15mp_priv_properties);
diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c
index d59e49126b..08346b0049 100644
--- a/hw/cpu/a9mpcore.c
+++ b/hw/cpu/a9mpcore.c
@@ -30,9 +30,6 @@ static void a9mp_priv_initfn(Object *obj)
{
A9MPPrivState *s = A9MPCORE_PRIV(obj);
- memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000);
- sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container);
-
object_initialize_child(obj, "scu", &s->scu, TYPE_A9_SCU);
object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
@@ -47,6 +44,7 @@ static void a9mp_priv_initfn(Object *obj)
static void a9mp_priv_realize(DeviceState *dev, Error **errp)
{
CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_GET_CLASS(dev);
+ CortexMPPrivState *c = CORTEX_MPCORE_PRIV(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
A9MPPrivState *s = A9MPCORE_PRIV(dev);
DeviceState *scudev, *gicdev, *gtimerdev, *mptimerdev, *wdtdev;
@@ -134,21 +132,21 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)
* 0x0700-0x0fff -- nothing
* 0x1000-0x1fff -- GIC Distributor
*/
- memory_region_add_subregion(&s->container, 0,
+ memory_region_add_subregion(&c->container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */
- memory_region_add_subregion(&s->container, 0x100,
+ memory_region_add_subregion(&c->container, 0x100,
sysbus_mmio_get_region(gicbusdev, 1));
- memory_region_add_subregion(&s->container, 0x200,
+ memory_region_add_subregion(&c->container, 0x200,
sysbus_mmio_get_region(gtimerbusdev, 0));
/* Note that the A9 exposes only the "timer/watchdog for this core"
* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
*/
- memory_region_add_subregion(&s->container, 0x600,
+ memory_region_add_subregion(&c->container, 0x600,
sysbus_mmio_get_region(mptimerbusdev, 0));
- memory_region_add_subregion(&s->container, 0x620,
+ memory_region_add_subregion(&c->container, 0x620,
sysbus_mmio_get_region(wdtbusdev, 0));
- memory_region_add_subregion(&s->container, 0x1000,
+ memory_region_add_subregion(&c->container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
/* Wire up the interrupt from each watchdog and timer.
@@ -183,6 +181,8 @@ static void a9mp_priv_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
CortexMPPrivClass *cc = CORTEX_MPCORE_PRIV_CLASS(klass);
+ cc->container_size = 0x2000;
+
device_class_set_parent_realize(dc, a9mp_priv_realize, &cc->parent_realize);
device_class_set_props(dc, a9mp_priv_properties);
}
diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c
index 7d3796bd69..0c12f99610 100644
--- a/hw/cpu/cortex_mpcore.c
+++ b/hw/cpu/cortex_mpcore.c
@@ -7,13 +7,27 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/cpu/cortex_mpcore.h"
+static void cortex_mpcore_priv_instance_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ CortexMPPrivState *s = CORTEX_MPCORE_PRIV(obj);
+ CortexMPPrivClass *k = CORTEX_MPCORE_PRIV_GET_CLASS(obj);
+
+ assert(k->container_size > 0);
+ memory_region_init(&s->container, obj,
+ "mpcore-priv-container", k->container_size);
+ sysbus_init_mmio(sbd, &s->container);
+}
+
static const TypeInfo cortex_mpcore_types[] = {
{
.name = TYPE_CORTEX_MPCORE_PRIV,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(CortexMPPrivState),
+ .instance_init = cortex_mpcore_priv_instance_init,
.class_size = sizeof(CortexMPPrivClass),
.abstract = true,
},
--
2.41.0
next prev parent reply other threads:[~2023-12-12 16:33 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 16:29 [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 01/33] hw/arm/boot: Propagate vCPU to arm_load_dtb() Philippe Mathieu-Daudé
2024-01-02 13:51 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 02/33] hw/arm/fsl-imx6: Add a local 'gic' variable Philippe Mathieu-Daudé
2024-01-02 13:52 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 03/33] hw/arm/fsl-imx6ul: " Philippe Mathieu-Daudé
2024-01-02 13:52 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 04/33] hw/arm/fsl-imx7: " Philippe Mathieu-Daudé
2024-01-02 13:53 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 05/33] hw/cpu: Remove dead Kconfig Philippe Mathieu-Daudé
2024-01-02 13:53 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 06/33] hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_realize() Philippe Mathieu-Daudé
2024-01-02 13:54 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 07/33] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Philippe Mathieu-Daudé
2024-01-02 13:57 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 08/33] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2024-01-02 13:57 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 09/33] hw/cpu/arm: Merge {a9mpcore.h, a15mpcore.h} as cortex_mpcore.h Philippe Mathieu-Daudé
2024-01-02 14:00 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 10/33] hw/cpu/arm: Introduce abstract CORTEX_MPCORE_PRIV QOM type Philippe Mathieu-Daudé
2024-01-02 14:23 ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 11/33] hw/cpu/arm: Have A9MPCORE/A15MPCORE inheritate common CORTEX_MPCORE_PRIV Philippe Mathieu-Daudé
2024-01-02 14:23 ` Cédric Le Goater
2023-12-12 16:29 ` Philippe Mathieu-Daudé [this message]
2024-01-02 14:23 ` [PATCH 12/33] hw/cpu/arm: Create MPCore container in QOM parent Cédric Le Goater
2023-12-12 16:29 ` [PATCH 13/33] hw/cpu/arm: Handle 'num_cores' property once in MPCore parent Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 14/33] hw/cpu/arm: Handle 'has_el2/3' properties " Philippe Mathieu-Daudé
2024-01-12 21:33 ` Fabiano Rosas
2024-01-16 16:25 ` Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 15/33] hw/cpu/arm: Handle 'gic-irq' property " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 16/33] hw/cpu/arm: Handle GIC " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 17/33] hw/cpu/arm: Document more properties of CORTEX_MPCORE_PRIV QOM type Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 18/33] hw/cpu/arm: Replace A15MPPrivState by CortexMPPrivState Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 19/33] hw/cpu/arm: Introduce TYPE_A7MPCORE_PRIV for Cortex-A7 MPCore Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 20/33] hw/cpu/arm: Consolidate check on max GIC spi supported Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 21/33] hw/cpu/arm: Create CPUs once in MPCore parent Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 22/33] hw/arm/aspeed_ast2600: Let the A7MPcore create/wire the CPU cores Philippe Mathieu-Daudé
2024-01-02 0:11 ` Andrew Jeffery
2023-12-12 16:29 ` [PATCH 23/33] hw/arm/exynos4210: Let the A9MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 24/33] hw/arm/fsl-imx6: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 25/33] hw/arm/fsl-imx6ul: Let the A7MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 26/33] hw/arm/fsl-imx7: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 27/33] hw/arm/highbank: Let the A9/A15MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 28/33] hw/arm/vexpress: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 29/33] hw/arm/xilinx_zynq: Let the A9MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 30/33] hw/arm/npcm7xx: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 31/33] hw/cpu/a9mpcore: Remove legacy code Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 32/33] hw/cpu/arm: Remove 'num-cpu' property alias Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 33/33] hw/cpu/arm: Remove use of qemu_get_cpu() in A7/A15 realize() Philippe Mathieu-Daudé
2023-12-26 11:17 ` [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv Philippe Mathieu-Daudé
2024-01-02 14:55 ` Cédric Le Goater
2024-01-02 16:15 ` Philippe Mathieu-Daudé
2024-01-02 16:41 ` Cédric Le Goater
2024-01-03 9:19 ` Philippe Mathieu-Daudé
2024-01-03 19:53 ` Fabiano Rosas
2024-01-09 15:02 ` Cédric Le Goater
2024-01-09 17:40 ` Fabiano Rosas
2024-01-09 18:06 ` Cédric Le Goater
2024-01-09 20:21 ` Fabiano Rosas
2024-01-09 21:22 ` Philippe Mathieu-Daudé
2024-01-10 3:36 ` Peter Xu
2024-01-10 6:03 ` Markus Armbruster
2024-01-10 6:26 ` Peter Xu
2024-01-10 8:09 ` Markus Armbruster
2024-01-10 8:44 ` Peter Xu
2024-01-12 9:03 ` Cédric Le Goater
2024-01-10 13:19 ` Fabiano Rosas
2024-01-10 13:54 ` Markus Armbruster
2024-01-12 10:26 ` Cédric Le Goater
2024-01-12 19:54 ` Fabiano Rosas
2024-01-15 9:04 ` Cédric Le Goater
2024-01-12 8:41 ` Cédric Le Goater
2024-01-09 21:07 ` Philippe Mathieu-Daudé
2024-01-09 21:09 ` Philippe Mathieu-Daudé
2024-01-12 8:00 ` Cédric Le Goater
2024-01-12 7:29 ` Cédric Le Goater
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