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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 24/33] hw/arm/fsl-imx6: Let the A9MPcore create/wire the CPU cores Date: Tue, 12 Dec 2023 17:29:24 +0100 Message-ID: <20231212162935.42910-25-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Set the properties on the a9mpcore object to let it create and wire the CPU cores. Remove the redundant code. Signed-off-by: Philippe Mathieu-Daudé --- include/hw/arm/fsl-imx6.h | 4 ---- hw/arm/fsl-imx6.c | 47 +++++++-------------------------------- hw/arm/sabrelite.c | 4 +++- 3 files changed, 11 insertions(+), 44 deletions(-) diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h index 21a3b035a4..643c3160c7 100644 --- a/include/hw/arm/fsl-imx6.h +++ b/include/hw/arm/fsl-imx6.h @@ -33,7 +33,6 @@ #include "hw/usb/chipidea.h" #include "hw/usb/imx-usb-phy.h" #include "exec/memory.h" -#include "cpu.h" #include "qom/object.h" #define TYPE_FSL_IMX6 "fsl-imx6" @@ -51,11 +50,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6State, FSL_IMX6) #define FSL_IMX6_NUM_USBS 4 struct FslIMX6State { - /*< private >*/ DeviceState parent_obj; - /*< public >*/ - ARMCPU cpu[FSL_IMX6_NUM_CPUS]; A9MPPrivState a9mpcore; IMX6CCMState ccm; IMX6SRCState src; diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 65c7c1a0f9..f05ea62351 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -29,6 +29,7 @@ #include "chardev/char.h" #include "qemu/error-report.h" #include "qemu/module.h" +#include "target/arm/cpu.h" #define IMX6_ESDHC_CAPABILITIES 0x057834b4 @@ -36,17 +37,10 @@ static void fsl_imx6_init(Object *obj) { - MachineState *ms = MACHINE(qdev_get_machine()); FslIMX6State *s = FSL_IMX6(obj); char name[NAME_SIZE]; int i; - for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) { - snprintf(name, NAME_SIZE, "cpu%d", i); - object_initialize_child(obj, name, &s->cpu[i], - ARM_CPU_TYPE_NAME("cortex-a9")); - } - object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV); object_initialize_child(obj, "ccm", &s->ccm, TYPE_IMX6_CCM); @@ -119,43 +113,18 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) return; } - for (i = 0; i < smp_cpus; i++) { - - /* On uniprocessor, the CBAR is set to 0 */ - if (smp_cpus > 1) { - object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", - FSL_IMX6_A9MPCORE_ADDR, &error_abort); - } - - /* All CPU but CPU 0 start in power off mode */ - if (i) { - object_property_set_bool(OBJECT(&s->cpu[i]), "start-powered-off", - true, &error_abort); - } - - if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { - return; - } - } - - object_property_set_int(OBJECT(&s->a9mpcore), "num-cores", smp_cpus, - &error_abort); - - object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", - FSL_IMX6_MAX_IRQ + GIC_INTERNAL, &error_abort); - + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cores", smp_cpus); + qdev_prop_set_string(DEVICE(&s->a9mpcore), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-a9")); + qdev_prop_set_uint64(DEVICE(&s->a9mpcore), "cpu-reset-cbar", + FSL_IMX6_A9MPCORE_ADDR); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "gic-spi-num", + FSL_IMX6_MAX_IRQ + GIC_INTERNAL); if (!sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), errp)) { return; } sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, FSL_IMX6_A9MPCORE_ADDR); - for (i = 0; i < smp_cpus; i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ)); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus, - qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ)); - } - if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) { return; } diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 56f184b9ae..751053e8e3 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -99,7 +99,9 @@ static void sabrelite_init(MachineState *machine) sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; if (!qtest_enabled()) { - arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo); + CortexMPPrivState *mp = CORTEX_MPCORE_PRIV(&s->a9mpcore); + + arm_load_kernel(mp->cpu[0], machine, &sabrelite_binfo); } } -- 2.41.0