qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Tyrone Ting" <kfting@nuvoton.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Manos Pitsidianakis" <manos.pitsidianakis@linaro.org>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Joel Stanley" <joel@jms.id.au>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Anton Johansson" <anjo@rev.ng>,
	"Andrey Smirnov" <andrew.smirnov@gmail.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Hao Wu" <wuhaotsh@google.com>, "Cédric Le Goater" <clg@kaod.org>,
	"Jean-Christophe Dubois" <jcd@tribudubois.net>,
	"Igor Mitsyanko" <i.mitsyanko@gmail.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Rob Herring" <robh@kernel.org>,
	qemu-arm@nongnu.org,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 02/33] hw/arm/fsl-imx6: Add a local 'gic' variable
Date: Tue, 12 Dec 2023 17:29:02 +0100	[thread overview]
Message-ID: <20231212162935.42910-3-philmd@linaro.org> (raw)
In-Reply-To: <20231212162935.42910-1-philmd@linaro.org>

The A9MPCore forward the IRQs from its internal GIC.
To make the code clearer, add a 'gic' variable.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/arm/fsl-imx6.c | 37 +++++++++++++------------------------
 1 file changed, 13 insertions(+), 24 deletions(-)

diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 7dc42cbfe6..f6edbd7465 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -111,6 +111,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
     uint16_t i;
     Error *err = NULL;
     unsigned int smp_cpus = ms->smp.cpus;
+    DeviceState *gic = DEVICE(&s->a9mpcore);
 
     if (smp_cpus > FSL_IMX6_NUM_CPUS) {
         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
@@ -186,8 +187,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            serial_table[i].irq));
+                           qdev_get_gpio_in(gic, serial_table[i].irq));
     }
 
     s->gpt.ccm = IMX_CCM(&s->ccm);
@@ -198,8 +198,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt), 0, FSL_IMX6_GPT_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpt), 0,
-                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                        FSL_IMX6_GPT_IRQ));
+                       qdev_get_gpio_in(gic, FSL_IMX6_GPT_IRQ));
 
     /* Initialize all EPIT timers */
     for (i = 0; i < FSL_IMX6_NUM_EPITS; i++) {
@@ -219,8 +218,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->epit[i]), 0, epit_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->epit[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            epit_table[i].irq));
+                           qdev_get_gpio_in(gic, epit_table[i].irq));
     }
 
     /* Initialize all I2C */
@@ -240,8 +238,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, i2c_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            i2c_table[i].irq));
+                           qdev_get_gpio_in(gic, i2c_table[i].irq));
     }
 
     /* Initialize all GPIOs */
@@ -298,11 +295,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, gpio_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            gpio_table[i].irq_low));
+                           qdev_get_gpio_in(gic, gpio_table[i].irq_low));
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 1,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            gpio_table[i].irq_high));
+                           qdev_get_gpio_in(gic, gpio_table[i].irq_high));
     }
 
     /* Initialize all SDHC */
@@ -329,8 +324,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
         }
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            esdhc_table[i].irq));
+                           qdev_get_gpio_in(gic, esdhc_table[i].irq));
     }
 
     /* USB */
@@ -351,8 +345,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
                         FSL_IMX6_USBOH3_USB_ADDR + i * 0x200);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            FSL_IMX6_USBn_IRQ[i]));
+                           qdev_get_gpio_in(gic, FSL_IMX6_USBn_IRQ[i]));
     }
 
     /* Initialize all ECSPI */
@@ -375,8 +368,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            spi_table[i].irq));
+                           qdev_get_gpio_in(gic, spi_table[i].irq));
     }
 
     object_property_set_uint(OBJECT(&s->eth), "phy-num", s->phy_num,
@@ -387,11 +379,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
     }
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth), 0, FSL_IMX6_ENET_ADDR);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 0,
-                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                        FSL_IMX6_ENET_MAC_IRQ));
+                       qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_IRQ));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth), 1,
-                       qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                        FSL_IMX6_ENET_MAC_1588_IRQ));
+                       qdev_get_gpio_in(gic, FSL_IMX6_ENET_MAC_1588_IRQ));
 
     /*
      * SNVS
@@ -418,8 +408,7 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
 
         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX6_WDOGn_ADDR[i]);
         sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0,
-                           qdev_get_gpio_in(DEVICE(&s->a9mpcore),
-                                            FSL_IMX6_WDOGn_IRQ[i]));
+                           qdev_get_gpio_in(gic, FSL_IMX6_WDOGn_IRQ[i]));
     }
 
     /* ROM memory */
-- 
2.41.0



  parent reply	other threads:[~2023-12-12 16:31 UTC|newest]

Thread overview: 76+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-12 16:29 [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 01/33] hw/arm/boot: Propagate vCPU to arm_load_dtb() Philippe Mathieu-Daudé
2024-01-02 13:51   ` Cédric Le Goater
2023-12-12 16:29 ` Philippe Mathieu-Daudé [this message]
2024-01-02 13:52   ` [PATCH 02/33] hw/arm/fsl-imx6: Add a local 'gic' variable Cédric Le Goater
2023-12-12 16:29 ` [PATCH 03/33] hw/arm/fsl-imx6ul: " Philippe Mathieu-Daudé
2024-01-02 13:52   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 04/33] hw/arm/fsl-imx7: " Philippe Mathieu-Daudé
2024-01-02 13:53   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 05/33] hw/cpu: Remove dead Kconfig Philippe Mathieu-Daudé
2024-01-02 13:53   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 06/33] hw/cpu/arm: Rename 'busdev' -> 'gicsbd' in a15mp_priv_realize() Philippe Mathieu-Daudé
2024-01-02 13:54   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 07/33] hw/cpu/arm: Alias 'num-cpu' property on TYPE_REALVIEW_MPCORE Philippe Mathieu-Daudé
2024-01-02 13:57   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 08/33] hw/cpu/arm: Declare CPU QOM types using DEFINE_TYPES() macro Philippe Mathieu-Daudé
2024-01-02 13:57   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 09/33] hw/cpu/arm: Merge {a9mpcore.h, a15mpcore.h} as cortex_mpcore.h Philippe Mathieu-Daudé
2024-01-02 14:00   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 10/33] hw/cpu/arm: Introduce abstract CORTEX_MPCORE_PRIV QOM type Philippe Mathieu-Daudé
2024-01-02 14:23   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 11/33] hw/cpu/arm: Have A9MPCORE/A15MPCORE inheritate common CORTEX_MPCORE_PRIV Philippe Mathieu-Daudé
2024-01-02 14:23   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 12/33] hw/cpu/arm: Create MPCore container in QOM parent Philippe Mathieu-Daudé
2024-01-02 14:23   ` Cédric Le Goater
2023-12-12 16:29 ` [PATCH 13/33] hw/cpu/arm: Handle 'num_cores' property once in MPCore parent Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 14/33] hw/cpu/arm: Handle 'has_el2/3' properties " Philippe Mathieu-Daudé
2024-01-12 21:33   ` Fabiano Rosas
2024-01-16 16:25     ` Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 15/33] hw/cpu/arm: Handle 'gic-irq' property " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 16/33] hw/cpu/arm: Handle GIC " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 17/33] hw/cpu/arm: Document more properties of CORTEX_MPCORE_PRIV QOM type Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 18/33] hw/cpu/arm: Replace A15MPPrivState by CortexMPPrivState Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 19/33] hw/cpu/arm: Introduce TYPE_A7MPCORE_PRIV for Cortex-A7 MPCore Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 20/33] hw/cpu/arm: Consolidate check on max GIC spi supported Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 21/33] hw/cpu/arm: Create CPUs once in MPCore parent Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 22/33] hw/arm/aspeed_ast2600: Let the A7MPcore create/wire the CPU cores Philippe Mathieu-Daudé
2024-01-02  0:11   ` Andrew Jeffery
2023-12-12 16:29 ` [PATCH 23/33] hw/arm/exynos4210: Let the A9MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 24/33] hw/arm/fsl-imx6: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 25/33] hw/arm/fsl-imx6ul: Let the A7MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 26/33] hw/arm/fsl-imx7: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 27/33] hw/arm/highbank: Let the A9/A15MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 28/33] hw/arm/vexpress: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 29/33] hw/arm/xilinx_zynq: Let the A9MPcore " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 30/33] hw/arm/npcm7xx: " Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 31/33] hw/cpu/a9mpcore: Remove legacy code Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 32/33] hw/cpu/arm: Remove 'num-cpu' property alias Philippe Mathieu-Daudé
2023-12-12 16:29 ` [PATCH 33/33] hw/cpu/arm: Remove use of qemu_get_cpu() in A7/A15 realize() Philippe Mathieu-Daudé
2023-12-26 11:17 ` [PATCH 00/33] hw/cpu/arm: Remove one use of qemu_get_cpu() in A7/A15 MPCore priv Philippe Mathieu-Daudé
2024-01-02 14:55 ` Cédric Le Goater
2024-01-02 16:15   ` Philippe Mathieu-Daudé
2024-01-02 16:41     ` Cédric Le Goater
2024-01-03  9:19       ` Philippe Mathieu-Daudé
2024-01-03 19:53         ` Fabiano Rosas
2024-01-09 15:02           ` Cédric Le Goater
2024-01-09 17:40             ` Fabiano Rosas
2024-01-09 18:06               ` Cédric Le Goater
2024-01-09 20:21                 ` Fabiano Rosas
2024-01-09 21:22                   ` Philippe Mathieu-Daudé
2024-01-10  3:36                     ` Peter Xu
2024-01-10  6:03                       ` Markus Armbruster
2024-01-10  6:26                         ` Peter Xu
2024-01-10  8:09                           ` Markus Armbruster
2024-01-10  8:44                             ` Peter Xu
2024-01-12  9:03                           ` Cédric Le Goater
2024-01-10 13:19                         ` Fabiano Rosas
2024-01-10 13:54                           ` Markus Armbruster
2024-01-12 10:26                           ` Cédric Le Goater
2024-01-12 19:54                             ` Fabiano Rosas
2024-01-15  9:04                               ` Cédric Le Goater
2024-01-12  8:41                         ` Cédric Le Goater
2024-01-09 21:07                 ` Philippe Mathieu-Daudé
2024-01-09 21:09                   ` Philippe Mathieu-Daudé
2024-01-12  8:00                     ` Cédric Le Goater
2024-01-12  7:29                   ` Cédric Le Goater

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20231212162935.42910-3-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=alex.bennee@linaro.org \
    --cc=alistair@alistair23.me \
    --cc=andrew.smirnov@gmail.com \
    --cc=andrew@codeconstruct.com.au \
    --cc=anjo@rev.ng \
    --cc=clg@kaod.org \
    --cc=edgar.iglesias@gmail.com \
    --cc=eduardo@habkost.net \
    --cc=i.mitsyanko@gmail.com \
    --cc=jcd@tribudubois.net \
    --cc=joel@jms.id.au \
    --cc=kfting@nuvoton.com \
    --cc=manos.pitsidianakis@linaro.org \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=robh@kernel.org \
    --cc=wuhaotsh@google.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).