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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 31/33] hw/cpu/a9mpcore: Remove legacy code Date: Tue, 12 Dec 2023 17:29:31 +0100 Message-ID: <20231212162935.42910-32-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that all boards set the "cpu-type" property, the legacy code can be removed. Signed-off-by: Philippe Mathieu-Daudé --- hw/cpu/a9mpcore.c | 8 +++----- hw/cpu/cortex_mpcore.c | 8 +++++--- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index ffdaf392fc..4e2fdb8321 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -41,12 +41,10 @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp) DeviceState *scudev, *gtimerdev, *mptimerdev, *wdtdev; SysBusDevice *scubusdev, *gtimerbusdev, *mptimerbusdev, *wdtbusdev; Error *local_err = NULL; - CPUState *cpu0; - Object *cpuobj; - cpu0 = qemu_get_cpu(0); - cpuobj = OBJECT(cpu0); - if (strcmp(object_get_typename(cpuobj), ARM_CPU_TYPE_NAME("cortex-a9"))) { + if (!c->cpu_type) { + qdev_prop_set_string(dev, "cpu-type", ARM_CPU_TYPE_NAME("cortex-a9")); + } else if (strcmp(c->cpu_type, ARM_CPU_TYPE_NAME("cortex-a9"))) { /* We might allow Cortex-A5 once we model it */ error_setg(errp, "Cortex-A9MPCore peripheral can only use Cortex-A9 CPU"); diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c index 65309636d7..c5de6c3ae4 100644 --- a/hw/cpu/cortex_mpcore.c +++ b/hw/cpu/cortex_mpcore.c @@ -57,6 +57,11 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, Error **errp) return; } + if (!s->cpu_type) { + error_setg(errp, "'cpu-type' property is not set"); + return; + } + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cores); qdev_prop_set_uint32(gicdev, "num-irq", s->gic_spi_num); if (k->gic_priority_bits) { @@ -85,9 +90,6 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, Error **errp) /* CPU */ - if (!s->cpu_type) { - return; - } for (int i = 0; i < s->num_cores; i++) { Object *cpuobj; -- 2.41.0