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Iglesias" , Andrew Jeffery , Rob Herring , qemu-arm@nongnu.org, Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 32/33] hw/cpu/arm: Remove 'num-cpu' property alias Date: Tue, 12 Dec 2023 17:29:32 +0100 Message-ID: <20231212162935.42910-33-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231212162935.42910-1-philmd@linaro.org> References: <20231212162935.42910-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All callers access the 'num-cores' property. Signed-off-by: Philippe Mathieu-Daudé --- Better to squash earlier and replace in place, so no need for alias? --- hw/cpu/arm11mpcore.c | 1 - hw/cpu/cortex_mpcore.c | 2 -- hw/cpu/realview_mpcore.c | 1 - 3 files changed, 4 deletions(-) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 67c96a3a7c..32756e05e9 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -133,7 +133,6 @@ static void mpcore_priv_initfn(Object *obj) static Property mpcore_priv_properties[] = { DEFINE_PROP_UINT32("num-cores", ARM11MPCorePriveState, num_cpu, 1), - DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), /* alias */ /* The ARM11 MPCORE TRM says the on-chip controller may have * anything from 0 to 224 external interrupt IRQ lines (with another * 32 internal). We default to 32+32, which is the number provided by diff --git a/hw/cpu/cortex_mpcore.c b/hw/cpu/cortex_mpcore.c index c5de6c3ae4..3cc9feef16 100644 --- a/hw/cpu/cortex_mpcore.c +++ b/hw/cpu/cortex_mpcore.c @@ -156,7 +156,6 @@ static void cortex_mpcore_priv_realize(DeviceState *dev, Error **errp) static Property cortex_mpcore_priv_properties[] = { DEFINE_PROP_UINT8("cluster-id", CortexMPPrivState, cluster_id, 0), DEFINE_PROP_UINT32("num-cores", CortexMPPrivState, num_cores, 1), - DEFINE_PROP_UINT32("num-cpu", CortexMPPrivState, num_cores, 1), /* alias */ DEFINE_PROP_STRING("cpu-type", CortexMPPrivState, cpu_type), DEFINE_PROP_BOOL("cpu-has-el3", CortexMPPrivState, cpu_has_el3, true), @@ -175,7 +174,6 @@ static Property cortex_mpcore_priv_properties[] = { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("gic-spi-num", CortexMPPrivState, gic_spi_num, 0), - DEFINE_PROP_UINT32("num-irq", CortexMPPrivState, gic_spi_num, 0), /* alias */ DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c index e985d230e0..4d4965126b 100644 --- a/hw/cpu/realview_mpcore.c +++ b/hw/cpu/realview_mpcore.c @@ -99,7 +99,6 @@ static void mpcore_rirq_init(Object *obj) object_initialize_child(obj, "a11priv", &s->priv, TYPE_ARM11MPCORE_PRIV); object_property_add_alias(obj, "num-cores", OBJECT(&s->priv), "num-cores"); - object_property_add_alias(obj, "num-cpu", OBJECT(&s->priv), "num-cores"); privbusdev = SYS_BUS_DEVICE(&s->priv); sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); -- 2.41.0