From: Nabih Estefan <nabihestefan@google.com>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, kfting@nuvoton.com,
wuhaotsh@google.com, jasowang@redhat.com,
avi.fishman@nuvoton.com, nabihestefan@google.com,
kwliu@nuvoton.com, tomer.maimon@nuvoton.com,
Hila.Miranda-Kuzi@nuvoton.com
Subject: [PATCH v8 05/11] hw/arm: Add GMAC devices to NPCM7XX SoC
Date: Thu, 14 Dec 2023 21:15:21 +0000 [thread overview]
Message-ID: <20231214211527.1946302-6-nabihestefan@google.com> (raw)
In-Reply-To: <20231214211527.1946302-1-nabihestefan@google.com>
From: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
---
hw/arm/npcm7xx.c | 36 ++++++++++++++++++++++++++++++++++--
include/hw/arm/npcm7xx.h | 2 ++
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index c9e87162cb..12e11250e1 100644
--- a/hw/arm/npcm7xx.c
+++ b/hw/arm/npcm7xx.c
@@ -91,6 +91,7 @@ enum NPCM7xxInterrupt {
NPCM7XX_GMAC1_IRQ = 14,
NPCM7XX_EMC1RX_IRQ = 15,
NPCM7XX_EMC1TX_IRQ,
+ NPCM7XX_GMAC2_IRQ,
NPCM7XX_MMC_IRQ = 26,
NPCM7XX_PSPI2_IRQ = 28,
NPCM7XX_PSPI1_IRQ = 31,
@@ -234,6 +235,12 @@ static const hwaddr npcm7xx_pspi_addr[] = {
0xf0201000,
};
+/* Register base address for each GMAC Module */
+static const hwaddr npcm7xx_gmac_addr[] = {
+ 0xf0802000,
+ 0xf0804000,
+};
+
static const struct {
hwaddr regs_addr;
uint32_t unconnected_pins;
@@ -462,6 +469,10 @@ static void npcm7xx_init(Object *obj)
object_initialize_child(obj, "pspi[*]", &s->pspi[i], TYPE_NPCM_PSPI);
}
+ for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
+ object_initialize_child(obj, "gmac[*]", &s->gmac[i], TYPE_NPCM_GMAC);
+ }
+
object_initialize_child(obj, "pci-mbox", &s->pci_mbox,
TYPE_NPCM7XX_PCI_MBOX);
object_initialize_child(obj, "mmc", &s->mmc, TYPE_NPCM7XX_SDHCI);
@@ -695,6 +706,29 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
}
+ /*
+ * GMAC Modules. Cannot fail.
+ */
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gmac_addr) != ARRAY_SIZE(s->gmac));
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->gmac) != 2);
+ for (i = 0; i < ARRAY_SIZE(s->gmac); i++) {
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]);
+
+ /*
+ * The device exists regardless of whether it's connected to a QEMU
+ * netdev backend. So always instantiate it even if there is no
+ * backend.
+ */
+ sysbus_realize(sbd, &error_abort);
+ sysbus_mmio_map(sbd, 0, npcm7xx_gmac_addr[i]);
+ int irq = i == 0 ? NPCM7XX_GMAC1_IRQ : NPCM7XX_GMAC2_IRQ;
+ /*
+ * N.B. The values for the second argument sysbus_connect_irq are
+ * chosen to match the registration order in npcm7xx_emc_realize.
+ */
+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, irq));
+ }
+
/*
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
* specified, but this is a programming error.
@@ -765,8 +799,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
- create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
- create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
index cec3792a2e..9e5cf639a2 100644
--- a/include/hw/arm/npcm7xx.h
+++ b/include/hw/arm/npcm7xx.h
@@ -30,6 +30,7 @@
#include "hw/misc/npcm7xx_pwm.h"
#include "hw/misc/npcm7xx_rng.h"
#include "hw/net/npcm7xx_emc.h"
+#include "hw/net/npcm_gmac.h"
#include "hw/nvram/npcm7xx_otp.h"
#include "hw/timer/npcm7xx_timer.h"
#include "hw/ssi/npcm7xx_fiu.h"
@@ -105,6 +106,7 @@ struct NPCM7xxState {
OHCISysBusState ohci;
NPCM7xxFIUState fiu[2];
NPCM7xxEMCState emc[2];
+ NPCMGMACState gmac[2];
NPCM7xxPCIMBoxState pci_mbox;
NPCM7xxSDHCIState mmc;
NPCMPSPIState pspi[2];
--
2.43.0.472.g3155946c3a-goog
next prev parent reply other threads:[~2023-12-14 21:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-14 21:15 [PATCH v8 00/11] Implementation of NPI Mailbox and GMAC Networking Module Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 01/11] hw/misc: Add Nuvoton's PCI Mailbox Module Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 02/11] hw/arm: Add PCI mailbox module to Nuvoton SoC Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 03/11] hw/misc: Add qtest for NPCM7xx PCI Mailbox Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 04/11] hw/net: Add NPCMXXX GMAC device Nabih Estefan
2023-12-14 21:15 ` Nabih Estefan [this message]
2023-12-14 21:15 ` [PATCH v8 06/11] tests/qtest: Creating qtest for GMAC Module Nabih Estefan
2023-12-18 14:28 ` Peter Maydell
2023-12-14 21:15 ` [PATCH v8 07/11] include/hw/net: Implemented Classes and Masks for GMAC Descriptors Nabih Estefan
2023-12-18 14:36 ` Peter Maydell
2023-12-14 21:15 ` [PATCH v8 08/11] hw/net: General GMAC Implementation Nabih Estefan
2023-12-18 14:38 ` Peter Maydell
2023-12-14 21:15 ` [PATCH v8 09/11] hw/net: GMAC Rx Implementation Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 10/11] hw/net: GMAC Tx Implementation Nabih Estefan
2023-12-14 21:15 ` [PATCH v8 11/11] tests/qtest: Adding PCS Module test to GMAC Qtest Nabih Estefan
2023-12-18 14:43 ` Peter Maydell
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