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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id f10-20020adff8ca000000b003365951cef9sm487520wrq.55.2023.12.15.05.14.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 05:14:19 -0800 (PST) Date: Fri, 15 Dec 2023 14:14:17 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH for-9.0 3/5] target/riscv/kvm: change timer regs size to u64 Message-ID: <20231215-3b911ad3431253fb4182b349@orel> References: <20231208183835.2411523-1-dbarboza@ventanamicro.com> <20231208183835.2411523-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231208183835.2411523-4-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 08, 2023 at 03:38:33PM -0300, Daniel Henrique Barboza wrote: > KVM_REG_RISCV_TIMER regs are always u64 according to the KVM API, but at > this moment we'll return u32 regs if we're running a RISCV32 target. > > Use the kvm_riscv_reg_id_u64() helper in RISCV_TIMER_REG() to fix it. > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 26 +++++++++++++------------- > 1 file changed, 13 insertions(+), 13 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 34ed82ebe5..476e5d4b3d 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -88,7 +88,7 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) > #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ > KVM_REG_RISCV_CSR_REG(name)) > > -#define RISCV_TIMER_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_TIMER, \ > +#define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ > KVM_REG_RISCV_TIMER_REG(name)) > > #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) > @@ -111,17 +111,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) > } \ > } while (0) > > -#define KVM_RISCV_GET_TIMER(cs, env, name, reg) \ > +#define KVM_RISCV_GET_TIMER(cs, name, reg) \ > do { \ > - int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ > + int ret = kvm_get_one_reg(cs, RISCV_TIMER_REG(name), ®); \ > if (ret) { \ > abort(); \ > } \ > } while (0) > > -#define KVM_RISCV_SET_TIMER(cs, env, name, reg) \ > +#define KVM_RISCV_SET_TIMER(cs, name, reg) \ > do { \ > - int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(env, name), ®); \ > + int ret = kvm_set_one_reg(cs, RISCV_TIMER_REG(name), ®); \ > if (ret) { \ > abort(); \ > } \ > @@ -649,10 +649,10 @@ static void kvm_riscv_get_regs_timer(CPUState *cs) > return; > } > > - KVM_RISCV_GET_TIMER(cs, env, time, env->kvm_timer_time); > - KVM_RISCV_GET_TIMER(cs, env, compare, env->kvm_timer_compare); > - KVM_RISCV_GET_TIMER(cs, env, state, env->kvm_timer_state); > - KVM_RISCV_GET_TIMER(cs, env, frequency, env->kvm_timer_frequency); > + KVM_RISCV_GET_TIMER(cs, time, env->kvm_timer_time); > + KVM_RISCV_GET_TIMER(cs, compare, env->kvm_timer_compare); > + KVM_RISCV_GET_TIMER(cs, state, env->kvm_timer_state); > + KVM_RISCV_GET_TIMER(cs, frequency, env->kvm_timer_frequency); > > env->kvm_timer_dirty = true; > } > @@ -666,8 +666,8 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) > return; > } > > - KVM_RISCV_SET_TIMER(cs, env, time, env->kvm_timer_time); > - KVM_RISCV_SET_TIMER(cs, env, compare, env->kvm_timer_compare); > + KVM_RISCV_SET_TIMER(cs, time, env->kvm_timer_time); > + KVM_RISCV_SET_TIMER(cs, compare, env->kvm_timer_compare); > > /* > * To set register of RISCV_TIMER_REG(state) will occur a error from KVM > @@ -676,7 +676,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) > * TODO If KVM changes, adapt here. > */ > if (env->kvm_timer_state) { > - KVM_RISCV_SET_TIMER(cs, env, state, env->kvm_timer_state); > + KVM_RISCV_SET_TIMER(cs, state, env->kvm_timer_state); > } > > /* > @@ -685,7 +685,7 @@ static void kvm_riscv_put_regs_timer(CPUState *cs) > * during the migration. > */ > if (migration_is_running(migrate_get_current()->state)) { > - KVM_RISCV_GET_TIMER(cs, env, frequency, reg); > + KVM_RISCV_GET_TIMER(cs, frequency, reg); > if (reg != env->kvm_timer_frequency) { > error_report("Dst Hosts timer frequency != Src Hosts"); > } > -- > 2.41.0 > Reviewed-by: Andrew Jones