From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH for-9.0 5/5] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong()
Date: Fri, 15 Dec 2023 14:19:37 +0100 [thread overview]
Message-ID: <20231215-45e97313ce6a97ed3eb9e8dd@orel> (raw)
In-Reply-To: <20231208183835.2411523-6-dbarboza@ventanamicro.com>
On Fri, Dec 08, 2023 at 03:38:35PM -0300, Daniel Henrique Barboza wrote:
> kvm_riscv_reg_id() returns an id encoded with an ulong size, i.e. an u32
> size when running TARGET_RISCV32 and u64 when running TARGET_RISCV64.
>
> Rename it to kvm_riscv_reg_id_ulong() to enhance code readability. It'll
> be in line with the existing kvm_riscv_reg_id_<size>() helpers.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/kvm/kvm-cpu.c | 40 ++++++++++++++++++++------------------
> 1 file changed, 21 insertions(+), 19 deletions(-)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index 11797338ec..62a1e51f0a 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -54,7 +54,7 @@ void riscv_kvm_aplic_request(void *opaque, int irq, int level)
>
> static bool cap_has_mp_state;
>
> -static uint64_t kvm_riscv_reg_id(CPURISCVState *env, uint64_t type,
> +static uint64_t kvm_riscv_reg_id_ulong(CPURISCVState *env, uint64_t type,
> uint64_t idx)
> {
> uint64_t id = KVM_REG_RISCV | type | idx;
> @@ -82,15 +82,17 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx)
> return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx;
> }
>
> -#define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \
> - KVM_REG_RISCV_CORE_REG(name))
> +#define RISCV_CORE_REG(env, name) \
> + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, \
> + KVM_REG_RISCV_CORE_REG(name))
>
> -#define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \
> - KVM_REG_RISCV_CSR_REG(name))
> +#define RISCV_CSR_REG(env, name) \
> + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CSR, \
> + KVM_REG_RISCV_CSR_REG(name))
>
> #define RISCV_CONFIG_REG(env, name) \
> - kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \
> - KVM_REG_RISCV_CONFIG_REG(name))
> + kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG, \
> + KVM_REG_RISCV_CONFIG_REG(name))
>
> #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \
> KVM_REG_RISCV_TIMER_REG(name))
> @@ -216,8 +218,8 @@ static void kvm_riscv_update_cpu_misa_ext(RISCVCPU *cpu, CPUState *cs)
>
> /* If we're here we're going to disable the MISA bit */
> reg = 0;
> - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT,
> - misa_cfg->kvm_reg_id);
> + id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
> + misa_cfg->kvm_reg_id);
> ret = kvm_set_one_reg(cs, id, ®);
> if (ret != 0) {
> /*
> @@ -378,8 +380,8 @@ static void kvm_riscv_update_cpu_cfg_isa_ext(RISCVCPU *cpu, CPUState *cs)
> continue;
> }
>
> - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT,
> - multi_ext_cfg->kvm_reg_id);
> + id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
> + multi_ext_cfg->kvm_reg_id);
> reg = kvm_cpu_cfg_get(cpu, multi_ext_cfg);
> ret = kvm_set_one_reg(cs, id, ®);
> if (ret != 0) {
> @@ -509,7 +511,7 @@ static int kvm_riscv_get_regs_core(CPUState *cs)
> env->pc = reg;
>
> for (i = 1; i < 32; i++) {
> - uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> + uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
> ret = kvm_get_one_reg(cs, id, ®);
> if (ret) {
> return ret;
> @@ -534,7 +536,7 @@ static int kvm_riscv_put_regs_core(CPUState *cs)
> }
>
> for (i = 1; i < 32; i++) {
> - uint64_t id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, i);
> + uint64_t id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CORE, i);
> reg = env->gpr[i];
> ret = kvm_set_one_reg(cs, id, ®);
> if (ret) {
> @@ -810,8 +812,8 @@ static void kvm_riscv_read_cbomz_blksize(RISCVCPU *cpu, KVMScratchCPU *kvmcpu,
> struct kvm_one_reg reg;
> int ret;
>
> - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG,
> - cbomz_cfg->kvm_reg_id);
> + reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_CONFIG,
> + cbomz_cfg->kvm_reg_id);
> reg.addr = (uint64_t)kvmconfig_get_cfg_addr(cpu, cbomz_cfg);
> ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®);
> if (ret != 0) {
> @@ -832,8 +834,8 @@ static void kvm_riscv_read_multiext_legacy(RISCVCPU *cpu,
> KVMCPUConfig *multi_ext_cfg = &kvm_multi_ext_cfgs[i];
> struct kvm_one_reg reg;
>
> - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_ISA_EXT,
> - multi_ext_cfg->kvm_reg_id);
> + reg.id = kvm_riscv_reg_id_ulong(env, KVM_REG_RISCV_ISA_EXT,
> + multi_ext_cfg->kvm_reg_id);
> reg.addr = (uint64_t)&val;
> ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®);
> if (ret != 0) {
> @@ -925,8 +927,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
>
> for (i = 0; i < ARRAY_SIZE(kvm_multi_ext_cfgs); i++) {
> multi_ext_cfg = &kvm_multi_ext_cfgs[i];
> - reg_id = kvm_riscv_reg_id(&cpu->env, KVM_REG_RISCV_ISA_EXT,
> - multi_ext_cfg->kvm_reg_id);
> + reg_id = kvm_riscv_reg_id_ulong(&cpu->env, KVM_REG_RISCV_ISA_EXT,
> + multi_ext_cfg->kvm_reg_id);
> reg_search = bsearch(®_id, reglist->reg, reglist->n,
> sizeof(uint64_t), uint64_cmp);
> if (!reg_search) {
> --
> 2.41.0
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
next prev parent reply other threads:[~2023-12-15 13:20 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-08 18:38 [PATCH for-9.0 0/5] target/riscv/kvm: fix KVM reg id sizes Daniel Henrique Barboza
2023-12-08 18:38 ` [PATCH for-9.0 1/5] target/riscv/kvm: change KVM_REG_RISCV_FP_F to u32 Daniel Henrique Barboza
2023-12-15 13:08 ` Andrew Jones
2023-12-08 18:38 ` [PATCH for-9.0 2/5] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Daniel Henrique Barboza
2023-12-15 13:11 ` Andrew Jones
2023-12-08 18:38 ` [PATCH for-9.0 3/5] target/riscv/kvm: change timer regs size " Daniel Henrique Barboza
2023-12-15 13:14 ` Andrew Jones
2023-12-08 18:38 ` [PATCH for-9.0 4/5] target/riscv/kvm: add RISCV_CONFIG_REG() Daniel Henrique Barboza
2023-12-15 13:18 ` Andrew Jones
2023-12-08 18:38 ` [PATCH for-9.0 5/5] target/riscv/kvm: rename riscv_reg_id() to riscv_reg_id_ulong() Daniel Henrique Barboza
2023-12-15 13:19 ` Andrew Jones [this message]
2023-12-18 0:09 ` [PATCH for-9.0 0/5] target/riscv/kvm: fix KVM reg id sizes Alistair Francis
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