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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id t15-20020a05600c198f00b0040c4620b9fasm20512056wmq.11.2023.12.15.05.18.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 05:18:44 -0800 (PST) Date: Fri, 15 Dec 2023 14:18:43 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH for-9.0 4/5] target/riscv/kvm: add RISCV_CONFIG_REG() Message-ID: <20231215-76ed2a549d7b92118b50eee8@orel> References: <20231208183835.2411523-1-dbarboza@ventanamicro.com> <20231208183835.2411523-5-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231208183835.2411523-5-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 08, 2023 at 03:38:34PM -0300, Daniel Henrique Barboza wrote: > Create a RISCV_CONFIG_REG() macro, similar to what other regs use, to > hide away some of the boilerplate. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 25 +++++++++++-------------- > 1 file changed, 11 insertions(+), 14 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 476e5d4b3d..11797338ec 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -88,6 +88,10 @@ static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) > #define RISCV_CSR_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CSR, \ > KVM_REG_RISCV_CSR_REG(name)) > > +#define RISCV_CONFIG_REG(env, name) \ > + kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, \ > + KVM_REG_RISCV_CONFIG_REG(name)) > + > #define RISCV_TIMER_REG(name) kvm_riscv_reg_id_u64(KVM_REG_RISCV_TIMER, \ > KVM_REG_RISCV_TIMER_REG(name)) > > @@ -756,24 +760,21 @@ static void kvm_riscv_init_machine_ids(RISCVCPU *cpu, KVMScratchCPU *kvmcpu) > struct kvm_one_reg reg; > int ret; > > - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(mvendorid)); > + reg.id = RISCV_CONFIG_REG(env, mvendorid); > reg.addr = (uint64_t)&cpu->cfg.mvendorid; > ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > if (ret != 0) { > error_report("Unable to retrieve mvendorid from host, error %d", ret); > } > > - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(marchid)); > + reg.id = RISCV_CONFIG_REG(env, marchid); > reg.addr = (uint64_t)&cpu->cfg.marchid; > ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > if (ret != 0) { > error_report("Unable to retrieve marchid from host, error %d", ret); > } > > - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(mimpid)); > + reg.id = RISCV_CONFIG_REG(env, mimpid); > reg.addr = (uint64_t)&cpu->cfg.mimpid; > ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > if (ret != 0) { > @@ -788,8 +789,7 @@ static void kvm_riscv_init_misa_ext_mask(RISCVCPU *cpu, > struct kvm_one_reg reg; > int ret; > > - reg.id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(isa)); > + reg.id = RISCV_CONFIG_REG(env, isa); > reg.addr = (uint64_t)&env->misa_ext_mask; > ret = ioctl(kvmcpu->cpufd, KVM_GET_ONE_REG, ®); > > @@ -1094,8 +1094,7 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) > uint64_t id; > int ret; > > - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(mvendorid)); > + id = RISCV_CONFIG_REG(env, mvendorid); > /* > * cfg.mvendorid is an uint32 but a target_ulong will > * be written. Assign it to a target_ulong var to avoid > @@ -1107,15 +1106,13 @@ static int kvm_vcpu_set_machine_ids(RISCVCPU *cpu, CPUState *cs) > return ret; > } > > - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(marchid)); > + id = RISCV_CONFIG_REG(env, marchid); > ret = kvm_set_one_reg(cs, id, &cpu->cfg.marchid); > if (ret != 0) { > return ret; > } > > - id = kvm_riscv_reg_id(env, KVM_REG_RISCV_CONFIG, > - KVM_REG_RISCV_CONFIG_REG(mimpid)); > + id = RISCV_CONFIG_REG(env, mimpid); > ret = kvm_set_one_reg(cs, id, &cpu->cfg.mimpid); > > return ret; > -- > 2.41.0 > Reviewed-by: Andrew Jones