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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id z20-20020a05600c0a1400b004064e3b94afsm31971271wmp.4.2023.12.15.05.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 15 Dec 2023 05:11:14 -0800 (PST) Date: Fri, 15 Dec 2023 14:11:13 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com Subject: Re: [PATCH for-9.0 2/5] target/riscv/kvm: change KVM_REG_RISCV_FP_D to u64 Message-ID: <20231215-fbdf34e111d91f94bc654a13@orel> References: <20231208183835.2411523-1-dbarboza@ventanamicro.com> <20231208183835.2411523-3-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231208183835.2411523-3-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Dec 08, 2023 at 03:38:32PM -0300, Daniel Henrique Barboza wrote: > KVM_REG_RISCV_FP_D regs are always u64 size. Using kvm_riscv_reg_id() in > RISCV_FP_D_REG() ends up encoding the wrong size if we're running with > TARGET_RISCV32. > > Create a new helper that returns a KVM ID with u64 size and use it with > RISCV_FP_D_REG(). > > Reported-by: Andrew Jones > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/kvm/kvm-cpu.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c > index 9bfbc4ac98..34ed82ebe5 100644 > --- a/target/riscv/kvm/kvm-cpu.c > +++ b/target/riscv/kvm/kvm-cpu.c > @@ -77,6 +77,11 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) > return KVM_REG_RISCV | KVM_REG_SIZE_U32 | type | idx; > } > > +static uint64_t kvm_riscv_reg_id_u64(uint64_t type, uint64_t idx) > +{ > + return KVM_REG_RISCV | KVM_REG_SIZE_U64 | type | idx; > +} > + > #define RISCV_CORE_REG(env, name) kvm_riscv_reg_id(env, KVM_REG_RISCV_CORE, \ > KVM_REG_RISCV_CORE_REG(name)) > > @@ -88,7 +93,7 @@ static uint64_t kvm_riscv_reg_id_u32(uint64_t type, uint64_t idx) > > #define RISCV_FP_F_REG(idx) kvm_riscv_reg_id_u32(KVM_REG_RISCV_FP_F, idx) > > -#define RISCV_FP_D_REG(env, idx) kvm_riscv_reg_id(env, KVM_REG_RISCV_FP_D, idx) > +#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id_u64(KVM_REG_RISCV_FP_D, idx) > > #define KVM_RISCV_GET_CSR(cs, env, csr, reg) \ > do { \ > @@ -579,7 +584,7 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) > if (riscv_has_ext(env, RVD)) { > uint64_t reg; > for (i = 0; i < 32; i++) { > - ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(env, i), ®); > + ret = kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); > if (ret) { > return ret; > } > @@ -613,7 +618,7 @@ static int kvm_riscv_put_regs_fp(CPUState *cs) > uint64_t reg; > for (i = 0; i < 32; i++) { > reg = env->fpr[i]; > - ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(env, i), ®); > + ret = kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); > if (ret) { > return ret; > } > -- > 2.41.0 > Reviewed-by: Andrew Jones afaict, we're also missing fcsr here. And watch out for D's fcsr, it's 32-bit, even though the rest of the registers are 64-bit. Thanks, drew