* [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV
@ 2023-12-15 2:33 LIU Zhiwei
2023-12-17 22:46 ` Alistair Francis
2023-12-17 22:54 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: LIU Zhiwei @ 2023-12-15 2:33 UTC (permalink / raw)
To: qemu-devel
Cc: Alistair.Francis, palmer, bin.meng, liwei1518, dbarboza,
qemu-riscv, LIU Zhiwei
If CPU does not implement the Vector extension, it usually means
mstatus vs hardwire to zero. So we should not allow write a
non-zero value to this field.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
target/riscv/csr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index fde7ce1a53..d1de6b2390 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1328,11 +1328,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
- MSTATUS_TW | MSTATUS_VS;
+ MSTATUS_TW;
if (riscv_has_ext(env, RVF)) {
mask |= MSTATUS_FS;
}
+ if (riscv_has_ext(env, RVV)) {
+ mask |= MSTATUS_VS;
+ }
if (xl != MXL_RV32 || env->debugger) {
if (riscv_has_ext(env, RVH)) {
--
2.25.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV
2023-12-15 2:33 [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV LIU Zhiwei
@ 2023-12-17 22:46 ` Alistair Francis
2023-12-17 22:54 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2023-12-17 22:46 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, Alistair.Francis, palmer, bin.meng, liwei1518,
dbarboza, qemu-riscv
On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> If CPU does not implement the Vector extension, it usually means
> mstatus vs hardwire to zero. So we should not allow write a
> non-zero value to this field.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fde7ce1a53..d1de6b2390 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1328,11 +1328,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> - MSTATUS_TW | MSTATUS_VS;
> + MSTATUS_TW;
>
> if (riscv_has_ext(env, RVF)) {
> mask |= MSTATUS_FS;
> }
> + if (riscv_has_ext(env, RVV)) {
> + mask |= MSTATUS_VS;
> + }
>
> if (xl != MXL_RV32 || env->debugger) {
> if (riscv_has_ext(env, RVH)) {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV
2023-12-15 2:33 [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV LIU Zhiwei
2023-12-17 22:46 ` Alistair Francis
@ 2023-12-17 22:54 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2023-12-17 22:54 UTC (permalink / raw)
To: LIU Zhiwei
Cc: qemu-devel, Alistair.Francis, palmer, bin.meng, liwei1518,
dbarboza, qemu-riscv
On Fri, Dec 15, 2023 at 12:34 PM LIU Zhiwei
<zhiwei_liu@linux.alibaba.com> wrote:
>
> If CPU does not implement the Vector extension, it usually means
> mstatus vs hardwire to zero. So we should not allow write a
> non-zero value to this field.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/csr.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index fde7ce1a53..d1de6b2390 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -1328,11 +1328,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
> mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
> MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
> MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
> - MSTATUS_TW | MSTATUS_VS;
> + MSTATUS_TW;
>
> if (riscv_has_ext(env, RVF)) {
> mask |= MSTATUS_FS;
> }
> + if (riscv_has_ext(env, RVV)) {
> + mask |= MSTATUS_VS;
> + }
>
> if (xl != MXL_RV32 || env->debugger) {
> if (riscv_has_ext(env, RVH)) {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-12-17 22:55 UTC | newest]
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2023-12-15 2:33 [PATCH 1/1] target/riscv: Not allow write mstatus_vs without RVV LIU Zhiwei
2023-12-17 22:46 ` Alistair Francis
2023-12-17 22:54 ` Alistair Francis
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