From: Nikita Ostrenkov <n.ostrenkov@gmail.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jean-Christophe Dubois <jcd@tribudubois.net>,
qemu-arm@nongnu.org, Nikita Ostrenkov <n.ostrenkov@gmail.com>
Subject: [PATCH] hw/arm: add cache controller for Freescale i.MX6
Date: Tue, 19 Dec 2023 10:55:10 +0000 [thread overview]
Message-ID: <20231219105510.4907-1-n.ostrenkov@gmail.com> (raw)
Signed-off-by: Nikita Ostrenkov <n.ostrenkov@gmail.com>
---
hw/arm/Kconfig | 1 +
hw/arm/fsl-imx6.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index 3ada335a24..386f06840c 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -536,6 +536,7 @@ config FSL_IMX6
select IMX_I2C
select IMX_USBPHY
select WDT_IMX2
+ select PL310 # cache controller
select SDHCI
config ASPEED_SOC
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 7dc42cbfe6..f56130a7a7 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -154,6 +154,9 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + smp_cpus,
qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
}
+
+ /* L2 cache controller */
+ sysbus_create_simple("l2x0", FSL_IMX6_PL310_ADDR, NULL);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ccm), errp)) {
return;
--
2.34.1
next reply other threads:[~2023-12-19 10:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-19 10:55 Nikita Ostrenkov [this message]
2023-12-19 16:08 ` [PATCH] hw/arm: add cache controller for Freescale i.MX6 Peter Maydell
2023-12-19 19:05 ` Nikita Ostrenkov
2024-01-04 16:36 ` Philippe Mathieu-Daudé
2024-01-05 16:24 ` Peter Maydell
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