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* [PATCH 0/2] Added the ability to delegate LCOFI to VS
@ 2023-12-21 11:36 Vadim Shakirov
  2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Vadim Shakirov @ 2023-12-21 11:36 UTC (permalink / raw)
  To: qemu-devel
  Cc: Vadim Shakirov, Palmer Dabbelt, Alistair Francis, Bin Meng,
	Weiwei Li, Daniel Henrique Barboza, Liu Zhiwei, qemu-riscv

This series of patches adds LCOFI delegation from HS-mode to VS-mode.

This possibility must be implemented, as in the AIA spec in section 6.3.2
it is indicated in table 6.1 that in the case when the hideleg bit is set,
the corresponding vsip bit is an alias to the corresponding sip bit, also
for enable registers.

Vadim Shakirov (2):
  target/riscv/csr: Rename groups of interrupts
  target/riscv/csr: Added the ability to delegate LCOFI to VS

 target/riscv/csr.c | 50 ++++++++++++++++++++++++++++++----------------
 1 file changed, 33 insertions(+), 17 deletions(-)

-- 
2.34.1



^ permalink raw reply	[flat|nested] 10+ messages in thread
* [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR
@ 2024-02-12 17:11 Irina Ryapolova
  2024-02-12 17:11 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
  0 siblings, 1 reply; 10+ messages in thread
From: Irina Ryapolova @ 2024-02-12 17:11 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, palmer, alistair.francis, bin.meng, liwei1518,
	dbarboza, zhiwei_liu, Irina Ryapolova

CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
for injecting interrupts into VS level in situations not fully supported by the
facilities described thus far, but only with more active involvement of the hypervisor.
(See riscv-interrupts-1.0: Interrupts at VS level)

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
---
 target/riscv/csr.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3585,6 +3585,21 @@ static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->hvictl = val & HVICTL_VALID_MASK;
+    if (env->hvictl & HVICTL_VTI)
+    {
+        uint32_t hviid = get_field(env->hvictl, HVICTL_IID);
+        uint32_t hviprio = get_field(env->hvictl, HVICTL_IPRIO);
+        /* the pair IID = 9, IPRIO = 0 generally to represent no interrupt in hvictl. */
+        if (!(hviid == IRQ_S_EXT && hviprio == 0)) {
+            uint64_t new_val = BIT(hviid) ;
+             if (new_val & S_MODE_INTERRUPTS) {
+                rmw_hvip64(env, csrno, NULL, new_val << 1, new_val << 1);
+            } else if (new_val & LOCAL_INTERRUPTS) {
+                rmw_hvip64(env, csrno, NULL, new_val, new_val);
+            }
+        }
+    }
+    
     return RISCV_EXCP_NONE;
 }
 
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread
* [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR
@ 2024-02-12 17:13 Irina Ryapolova
  2024-02-12 17:13 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
  0 siblings, 1 reply; 10+ messages in thread
From: Irina Ryapolova @ 2024-02-12 17:13 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, palmer, alistair.francis, bin.meng, liwei1518,
	dbarboza, zhiwei_liu, Irina Ryapolova

CSR hvictl (Hypervisor Virtual Interrupt Control) provides further flexibility
for injecting interrupts into VS level in situations not fully supported by the
facilities described thus far, but only with more active involvement of the hypervisor.
(See riscv-interrupts-1.0: Interrupts at VS level)

Signed-off-by: Irina Ryapolova <irina.ryapolova@syntacore.com>
---
 target/riscv/csr.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 674ea075a4..0c21145eaf 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3585,6 +3585,21 @@ static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->hvictl = val & HVICTL_VALID_MASK;
+    if (env->hvictl & HVICTL_VTI)
+    {
+        uint32_t hviid = get_field(env->hvictl, HVICTL_IID);
+        uint32_t hviprio = get_field(env->hvictl, HVICTL_IPRIO);
+        /* the pair IID = 9, IPRIO = 0 generally to represent no interrupt in hvictl. */
+        if (!(hviid == IRQ_S_EXT && hviprio == 0)) {
+            uint64_t new_val = BIT(hviid) ;
+             if (new_val & S_MODE_INTERRUPTS) {
+                rmw_hvip64(env, csrno, NULL, new_val << 1, new_val << 1);
+            } else if (new_val & LOCAL_INTERRUPTS) {
+                rmw_hvip64(env, csrno, NULL, new_val, new_val);
+            }
+        }
+    }
+    
     return RISCV_EXCP_NONE;
 }
 
-- 
2.25.1



^ permalink raw reply related	[flat|nested] 10+ messages in thread
end of thread, other threads:[~2024-02-15  9:47 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-12-21 11:36 [PATCH 0/2] Added the ability to delegate LCOFI to VS Vadim Shakirov
2023-12-21 11:36 ` [PATCH 1/2] target/riscv/csr: Rename groups of interrupts Vadim Shakirov
2023-12-21 16:03   ` Daniel Henrique Barboza
2023-12-21 11:36 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Vadim Shakirov
2023-12-21 16:03   ` Daniel Henrique Barboza
2024-01-04  3:54 ` [PATCH 0/2] " Alistair Francis
2024-01-15  9:59   ` Vadim Shakirov
  -- strict thread matches above, loose matches on Subject: below --
2024-02-12 17:11 [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR Irina Ryapolova
2024-02-12 17:11 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova
2024-02-15  9:46   ` Alistair Francis
2024-02-12 17:13 [PATCH 1/2] target/riscv/csr.c: Add functional of hvictl CSR Irina Ryapolova
2024-02-12 17:13 ` [PATCH 2/2] target/riscv/csr: Added the ability to delegate LCOFI to VS Irina Ryapolova

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