From: Paolo Bonzini <pbonzini@redhat.com>
To: qemu-devel@nongnu.org
Cc: richard.henderson@linaro.org, mcb30@ipxe.org, qemu-stable@nongnu.org
Subject: [PATCH 5/5] target/i386: leave the A20 bit set in the final NPT walk
Date: Fri, 22 Dec 2023 18:59:51 +0100 [thread overview]
Message-ID: <20231222175951.172669-6-pbonzini@redhat.com> (raw)
In-Reply-To: <20231222175951.172669-1-pbonzini@redhat.com>
The A20 mask is only applied to the final memory access. Nested
page tables are always walked with the raw guest-physical address.
Unlike the previous patch, in this one the masking must be kept, but
it was done too early.
Cc: qemu-stable@nongnu.org
Fixes: 4a1e9d4d11c ("target/i386: Use atomic operations for pte updates", 2022-10-18)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/sysemu/excp_helper.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c
index ede8ba6b80e..37e650c1fcd 100644
--- a/target/i386/tcg/sysemu/excp_helper.c
+++ b/target/i386/tcg/sysemu/excp_helper.c
@@ -134,7 +134,6 @@ static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
static bool mmu_translate(CPUX86State *env, const TranslateParams *in,
TranslateResult *out, TranslateFault *err)
{
- const int32_t a20_mask = x86_get_a20_mask(env);
const target_ulong addr = in->addr;
const int pg_mode = in->pg_mode;
const bool is_user = (in->mmu_idx == MMU_USER_IDX);
@@ -417,10 +416,13 @@ do_check_protect_pse36:
}
}
- /* align to page_size */
- paddr = (pte & a20_mask & PG_ADDRESS_MASK & ~(page_size - 1))
- | (addr & (page_size - 1));
+ /* merge offset within page */
+ paddr = (pte & PG_ADDRESS_MASK & ~(page_size - 1)) | (addr & (page_size - 1));
+ /*
+ * Note that NPT is walked (for both paging structures and final guest
+ * addresses) using the address with the A20 bit set.
+ */
if (in->ptw_idx == MMU_NESTED_IDX) {
CPUTLBEntryFull *full;
int flags, nested_page_size;
@@ -459,7 +461,7 @@ do_check_protect_pse36:
}
}
- out->paddr = paddr;
+ out->paddr = paddr & x86_get_a20_mask(env);
out->prot = prot;
out->page_size = page_size;
return true;
--
2.43.0
prev parent reply other threads:[~2023-12-22 18:01 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-22 17:59 [PATCH 0/5] target/i386: Fix physical address masking bugs Paolo Bonzini
2023-12-22 17:59 ` [PATCH 1/5] target/i386: mask high bits of CR3 in 32-bit mode Paolo Bonzini
2023-12-25 20:33 ` Richard Henderson
2024-01-18 8:04 ` Michael Tokarev
2024-01-23 11:11 ` Paolo Bonzini
2023-12-22 17:59 ` [PATCH 2/5] target/i386: check validity of VMCB addresses Paolo Bonzini
2023-12-22 17:59 ` [PATCH 3/5] target/i386: Fix physical address truncation Paolo Bonzini
2023-12-23 10:34 ` Michael Brown
2023-12-23 11:47 ` Paolo Bonzini
2023-12-28 16:00 ` Michael Brown
2023-12-22 17:59 ` [PATCH 4/5] target/i386: remove unnecessary/wrong application of the A20 mask Paolo Bonzini
2023-12-22 17:59 ` Paolo Bonzini [this message]
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