From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: Re: [PATCH v13 00/26] riscv: RVA22 profiles support
Date: Tue, 2 Jan 2024 16:12:21 +0100 [thread overview]
Message-ID: <20240102-72dbc203ded50b48a3aebb76@orel> (raw)
In-Reply-To: <a3f0392c-6a1a-4d48-8d55-13348457c345@ventanamicro.com>
On Tue, Jan 02, 2024 at 08:40:48AM -0300, Daniel Henrique Barboza wrote:
> Hi,
>
> Drew brought to my attention the following post on the tech-unprivileged mailing
> list:
>
> "Architecture Review Committee meeting minutes, 12/19/23"
> https://lists.riscv.org/g/tech-unprivileged/message/611
>
> Second paragraph mentions:
>
> "In response to some recent discussion in the Apps and Tools HC about how profiles should
> be represented in GCC/LLVM, the ARC provides this answer: compilers should use a single parameter
> for an ISA string. An ISA string begins with either a base ISA name (e.g. rv64i) or a profile name
> (e.g. rva23u64) and is optionally followed by additional extensions (e.g. rv64imac_zicond or
> rva23u64_zfh_zicond). If the ISA string begins with a profile name, it is equivalent to
> replacing the profile name with its mandatory base ISA and its mandatory extensions; any
> optional extensions in a profile must be explicitly named if their inclusion is desired.
> ISAs are sets, and concatenating strings takes the union, so redundancy is legal (e.g.
> rva23u64, rva23u64_zicsr, and rva23u64_zicsr_zicsr are all valid and equivalent)."
>
> The takeaways from it:
>
> - this implementation is compliant with how profiles are interpreted, i.e. a profile is
> considered a set of the mandatory base ISA and mandatory extensions, and any additional/optional
> extensions must be explicitly named;
Yes, it's good QEMU's RISC-V CPU model command line will be consistent
with the above paragraph (and then presumably with RISC-V compiler
"ISA strings")
>
> - our ISA string format is also since we use the base ISA name + extensions format already.
> This series don't change/add anything in this regard.
>
>
> If we have enough demand for it, I can do a follow-up to add support for the ISA string
> profile format. I.e. this:
>
> $ build/qemu-system-riscv64 -M virt -cpu rva22s64 (...)
>
> # cat /proc/device-tree/cpus/cpu@0/riscv,isa
> rv64imafdc_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihintpause_zihpm_zfhmin_zca_zcd_zba_zbb_zbs_zkt_svinval_svpbmt
>
> Would become this:
>
> # cat /proc/device-tree/cpus/cpu@0/riscv,isa
> rva22s64
We can't do that. The "ISA string" referred to in the above command line
isn't the ISA string specified in "ISA Extension Naming Conventions" of
the unpriv spec, it's the string given to the compiler to tell it which
extensions it may assume when generating instructions.
Thanks,
drew
next prev parent reply other threads:[~2024-01-02 15:13 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-18 12:53 [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 01/26] target/riscv: create TYPE_RISCV_VENDOR_CPU Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 02/26] target/riscv/tcg: do not use "!generic" CPU checks Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 03/26] target/riscv/tcg: update priv_ver on user_set extensions Daniel Henrique Barboza
2024-01-04 4:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 04/26] target/riscv: add rv64i CPU Daniel Henrique Barboza
2024-01-04 4:11 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 05/26] target/riscv: add zicbop extension flag Daniel Henrique Barboza
2024-01-04 4:12 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 06/26] target/riscv/tcg: add 'zic64b' support Daniel Henrique Barboza
2024-01-04 5:00 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 07/26] riscv-qmp-cmds.c: expose named features in cpu_model_expansion Daniel Henrique Barboza
2024-01-04 5:13 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 08/26] target/riscv: add rva22u64 profile definition Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 09/26] target/riscv/kvm: add 'rva22u64' flag as unavailable Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 10/26] target/riscv/tcg: add user flag for profile support Daniel Henrique Barboza
2024-01-04 6:19 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 11/26] target/riscv/tcg: add MISA user options hash Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 12/26] target/riscv/tcg: add riscv_cpu_write_misa_bit() Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 13/26] target/riscv/tcg: handle profile MISA bits Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 14/26] target/riscv/tcg: add hash table insert helpers Daniel Henrique Barboza
2024-01-04 6:25 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 15/26] target/riscv/tcg: honor user choice for G MISA bits Daniel Henrique Barboza
2023-12-18 12:53 ` [PATCH v13 16/26] target/riscv/tcg: validate profiles during finalize Daniel Henrique Barboza
2024-01-04 6:27 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 17/26] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion Daniel Henrique Barboza
2024-01-04 6:29 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 18/26] target/riscv: add 'rva22u64' CPU Daniel Henrique Barboza
2024-01-04 6:31 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 19/26] target/riscv: implement svade Daniel Henrique Barboza
2024-01-04 22:59 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 20/26] target/riscv: add priv ver restriction to profiles Daniel Henrique Barboza
2024-01-04 23:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 21/26] target/riscv/cpu.c: finalize satp_mode earlier Daniel Henrique Barboza
2024-01-04 23:02 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 22/26] target/riscv/cpu.c: add riscv_cpu_is_32bit() Daniel Henrique Barboza
2024-01-04 23:04 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 23/26] target/riscv: add satp_mode profile support Daniel Henrique Barboza
2024-01-04 23:07 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 24/26] target/riscv: add 'parent' in profile description Daniel Henrique Barboza
2024-01-05 2:21 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 25/26] target/riscv: add RVA22S64 profile Daniel Henrique Barboza
2024-01-05 2:24 ` Alistair Francis
2023-12-18 12:53 ` [PATCH v13 26/26] target/riscv: add rva22s64 cpu Daniel Henrique Barboza
2024-01-05 2:25 ` Alistair Francis
2024-01-02 11:40 ` [PATCH v13 00/26] riscv: RVA22 profiles support Daniel Henrique Barboza
2024-01-02 15:12 ` Andrew Jones [this message]
2024-01-05 2:39 ` Alistair Francis
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