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From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Eduardo Habkost <eduardo@habkost.net>,
	Bernhard Beschow <shentey@gmail.com>
Subject: [PATCH 1/2] hw/i386/x86: Fix PIC interrupt handling if APIC globally disabled
Date: Wed,  3 Jan 2024 09:48:59 +0100	[thread overview]
Message-ID: <20240103084900.22856-2-shentey@gmail.com> (raw)
In-Reply-To: <20240103084900.22856-1-shentey@gmail.com>

QEMU populates the apic_state attribute of x86 CPUs if supported by real
hardware. Even when the APIC is globally disabled by a guest, this attribute
stays populated. This means that the APIC code paths are still used in this
case. However, chapter 10.4.3 of [1] requires that:

  When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent to an
  IA-32 processor without an on-chip APIC. The CPUID feature flag for the APIC
  [...] is also set to 0.

Fix this by checking the APIC feature flag rather than apic_state when deciding
whether PIC or APIC behavior is required. This fixes some real-world BIOSes.

Notice that presence of the CPUID_APIC flag implies that apic_state is non-NULL.

[1] Intel 64 and IA-32 Architectures Software Developer's Manual, Vol. 3A:
    System Programming Guide, Part 1

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
 hw/i386/x86.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 2b6291ad8d..a753d1aeca 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -516,10 +516,10 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp)
     CPU_FOREACH(cs) {
         X86CPU *cpu = X86_CPU(cs);
 
-        if (!cpu->apic_state) {
-            cpu_interrupt(cs, CPU_INTERRUPT_NMI);
-        } else {
+        if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC) {
             apic_deliver_nmi(cpu->apic_state);
+        } else {
+            cpu_interrupt(cs, CPU_INTERRUPT_NMI);
         }
     }
 }
@@ -551,8 +551,8 @@ static void pic_irq_request(void *opaque, int irq, int level)
     X86CPU *cpu = X86_CPU(cs);
 
     trace_x86_pic_interrupt(irq, level);
-    if (cpu->apic_state && !kvm_irqchip_in_kernel() &&
-        !whpx_apic_in_platform()) {
+    if ((cpu->env.features[FEAT_1_EDX] & CPUID_APIC) &&
+        !kvm_irqchip_in_kernel() && !whpx_apic_in_platform()) {
         CPU_FOREACH(cs) {
             cpu = X86_CPU(cs);
             if (apic_accept_pic_intr(cpu->apic_state)) {
-- 
2.43.0



  reply	other threads:[~2024-01-03  8:50 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-03  8:48 [PATCH 0/2] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled Bernhard Beschow
2024-01-03  8:48 ` Bernhard Beschow [this message]
2024-01-03  9:12   ` [PATCH 1/2] hw/i386/x86: Fix PIC interrupt handling if APIC " Alex Bennée
2024-01-03 17:36     ` Bernhard Beschow
2024-01-03  8:49 ` [PATCH 2/2] target/i386/cpu: Fix small typo in comment Bernhard Beschow
2024-01-03  9:07   ` Alex Bennée

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