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[77.11.174.94]) by smtp.gmail.com with ESMTPSA id 3-20020a508e03000000b0055515b40464sm2159752edw.81.2024.01.06.05.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 06 Jan 2024 05:25:55 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Eduardo Habkost , Richard Henderson , Paolo Bonzini , Marcel Apfelbaum , Bernhard Beschow Subject: [PATCH v2 0/3] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled Date: Sat, 6 Jan 2024 14:25:43 +0100 Message-ID: <20240106132546.21248-1-shentey@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series is part of my work emulating the VIA Apollo Pro 133T chipset in= QEMU=0D [1] and testing it by running real-world BIOSes on it. The first two patche= s fix=0D an issue regarding PIC interrupt handling, the third one just fixes a typo = in a=0D comment.=0D =0D During testing, I've found that the boot process gets stuck for some BIOSes= that=0D disable the LAPIC globally (by disabling the enable bit in the base address= =0D register). QEMU seems to emulate PIC interrupt handling only if a CPU doesn= 't=0D have a LAPIC, and always emulates LAPIC interrupt handling if one is presen= t.=0D According to the Intel documentation, a CPU should resort to PIC interrupt= =0D handling if its LAPIC is globally didabled. This series fixes this corner c= ase=0D which makes the boot process succeed. More details can be found in the comm= it=0D message.=0D =0D Testing done:=0D * `make check`=0D * `make check-avocado`=0D =0D v2:=0D * Pick up R-b tag=0D * Split and rework interrupt handling patch to consider i486 SMP systems. T= his=0D required dropping Alex' R-b tag.=0D =0D [1] https://github.com/shentok/qemu/tree/via-apollo-pro-133t=0D =0D Bernhard Beschow (3):=0D hw/i386/x86: Reverse if statement=0D hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled=0D target/i386/cpu: Fix typo in comment=0D =0D include/hw/i386/apic.h | 1 +=0D hw/i386/x86.c | 8 ++++----=0D hw/intc/apic_common.c | 13 +++++++++++++=0D target/i386/cpu.c | 2 +-=0D 4 files changed, 19 insertions(+), 5 deletions(-)=0D =0D -- =0D 2.43.0=0D =0D