From: Zhao Liu <zhao1.liu@linux.intel.com>
To: Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Zhao Liu <zhao1.liu@intel.com>,
Yanan Wang <wangyanan55@huawei.com>,
Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>
Subject: [PATCH v7 11/16] tests: Add test case of APIC ID for module level parsing
Date: Mon, 8 Jan 2024 16:27:22 +0800 [thread overview]
Message-ID: <20240108082727.420817-12-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20240108082727.420817-1-zhao1.liu@linux.intel.com>
From: Zhuocheng Ding <zhuocheng.ding@intel.com>
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding <zhuocheng.ding@intel.com>
Co-developed-by: Zhao Liu <zhao1.liu@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Yanan Wang <wangyanan55@huawei.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/unit/test-x86-topo.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/tests/unit/test-x86-topo.c b/tests/unit/test-x86-topo.c
index f21b8a5d95c2..55b731ccae55 100644
--- a/tests/unit/test-x86-topo.c
+++ b/tests/unit/test-x86-topo.c
@@ -37,6 +37,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 0);
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 0);
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
topo_info = (X86CPUTopoInfo) {1, 1, 1, 1};
@@ -74,13 +75,22 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 33, 2};
g_assert_cmpuint(apicid_core_width(&topo_info), ==, 6);
- topo_info = (X86CPUTopoInfo) {1, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 7, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 8, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 3);
+ topo_info = (X86CPUTopoInfo) {1, 9, 30, 2};
+ g_assert_cmpuint(apicid_module_width(&topo_info), ==, 4);
+
+ topo_info = (X86CPUTopoInfo) {1, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 0);
- topo_info = (X86CPUTopoInfo) {2, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {2, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 1);
- topo_info = (X86CPUTopoInfo) {3, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {3, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
- topo_info = (X86CPUTopoInfo) {4, 1, 30, 2};
+ topo_info = (X86CPUTopoInfo) {4, 6, 30, 2};
g_assert_cmpuint(apicid_die_width(&topo_info), ==, 2);
/* build a weird topology and see if IDs are calculated correctly
@@ -91,6 +101,7 @@ static void test_topo_bits(void)
topo_info = (X86CPUTopoInfo) {1, 1, 6, 3};
g_assert_cmpuint(apicid_smt_width(&topo_info), ==, 2);
g_assert_cmpuint(apicid_core_offset(&topo_info), ==, 2);
+ g_assert_cmpuint(apicid_module_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_die_offset(&topo_info), ==, 5);
g_assert_cmpuint(apicid_pkg_offset(&topo_info), ==, 5);
--
2.34.1
next prev parent reply other threads:[~2024-01-08 8:16 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 8:27 [PATCH v7 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
2024-01-08 8:27 ` [PATCH v7 01/16] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2024-01-08 8:27 ` [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2024-01-10 9:31 ` Xiaoyao Li
2024-01-11 8:43 ` Zhao Liu
2024-01-14 14:11 ` Xiaoyao Li
2024-01-15 3:04 ` Zhao Liu
2024-01-15 3:51 ` Xiaoyao Li
2024-01-15 4:16 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 03/16] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2024-01-10 11:52 ` Xiaoyao Li
2024-01-11 8:46 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 04/16] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2024-01-08 8:27 ` [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2024-01-11 3:19 ` Xiaoyao Li
2024-01-11 9:07 ` Zhao Liu
2024-01-23 9:56 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 06/16] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2024-01-08 8:27 ` [PATCH v7 07/16] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2024-01-11 5:53 ` Xiaoyao Li
2024-01-11 9:18 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F] Zhao Liu
2024-01-11 6:04 ` Xiaoyao Li
2024-01-11 9:21 ` Zhao Liu
2024-01-15 3:25 ` Yuan Yao
2024-01-15 4:09 ` Zhao Liu
2024-01-15 4:34 ` Xiaoyao Li
2024-01-15 5:20 ` Yuan Yao
2024-01-15 6:20 ` Zhao Liu
2024-01-15 6:57 ` Yuan Yao
2024-01-15 7:20 ` Zhao Liu
2024-01-15 9:03 ` Yuan Yao
2024-01-15 6:12 ` Zhao Liu
2024-01-15 6:11 ` Xiaoyao Li
2024-01-15 6:35 ` Zhao Liu
2024-01-15 7:16 ` Xiaoyao Li
2024-01-15 15:46 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 09/16] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2024-01-14 12:42 ` Xiaoyao Li
2024-01-15 3:52 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2024-01-14 13:49 ` Xiaoyao Li
2024-01-15 3:27 ` Zhao Liu
2024-01-15 4:18 ` Xiaoyao Li
2024-01-15 5:59 ` Zhao Liu
2024-01-15 7:45 ` Xiaoyao Li
2024-01-15 15:18 ` Zhao Liu
2024-01-16 16:40 ` Xiaoyao Li
2024-01-19 7:59 ` Zhao Liu
2024-01-26 3:37 ` Zhao Liu
2024-01-08 8:27 ` Zhao Liu [this message]
2024-01-08 8:27 ` [PATCH v7 12/16] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2024-01-08 8:27 ` [PATCH v7 13/16] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2024-01-08 8:27 ` [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2024-01-14 14:31 ` Xiaoyao Li
2024-01-15 3:40 ` Zhao Liu
2024-01-15 4:25 ` Xiaoyao Li
2024-01-15 6:25 ` Zhao Liu
2024-01-15 7:00 ` Xiaoyao Li
2024-01-15 14:55 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-01-14 14:42 ` Xiaoyao Li
2024-01-15 3:48 ` Zhao Liu
2024-01-15 4:27 ` Xiaoyao Li
2024-01-15 14:54 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 16/16] i386: Use CPUCacheInfo.share_level to encode " Zhao Liu
2024-01-08 17:46 ` [PATCH v7 00/16] Support smp.clusters for x86 in QEMU Moger, Babu
2024-01-09 1:48 ` Zhao Liu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240108082727.420817-12-zhao1.liu@linux.intel.com \
--to=zhao1.liu@linux.intel.com \
--cc=babu.moger@amd.com \
--cc=eduardo@habkost.net \
--cc=kvm@vger.kernel.org \
--cc=marcel.apfelbaum@gmail.com \
--cc=mst@redhat.com \
--cc=mtosatti@redhat.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wangyanan55@huawei.com \
--cc=yongwei.ma@intel.com \
--cc=zhao1.liu@intel.com \
--cc=zhenyu.z.wang@intel.com \
--cc=zhuocheng.ding@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).