From: Zhao Liu <zhao1.liu@linux.intel.com>
To: Eduardo Habkost <eduardo@habkost.net>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
"Michael S . Tsirkin" <mst@redhat.com>,
Richard Henderson <richard.henderson@linaro.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Marcelo Tosatti <mtosatti@redhat.com>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Zhao Liu <zhao1.liu@intel.com>, Babu Moger <babu.moger@amd.com>,
Yongwei Ma <yongwei.ma@intel.com>
Subject: [PATCH v7 16/16] i386: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14]
Date: Mon, 8 Jan 2024 16:27:27 +0800 [thread overview]
Message-ID: <20240108082727.420817-17-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20240108082727.420817-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x8000001D].EAX[bits 25:14].
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
Changes since v3:
* Explain what "CPUID[0x8000001D].EAX[bits 25:14]" means in the commit
message. (Babu)
Changes since v1:
* Use cache->share_level as the parameter in
max_processor_ids_for_cache().
---
target/i386/cpu.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 8a4d72f6f760..4688b5d584bb 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -483,20 +483,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t num_sharing_cache;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
-
- /* L3 is shared among multiple cores */
- if (cache->level == 3) {
- num_sharing_cache = 1 << apicid_die_offset(topo_info);
- } else {
- num_sharing_cache = 1 << apicid_core_offset(topo_info);
- }
- *eax |= (num_sharing_cache - 1) << 14;
+ *eax |= max_processor_ids_for_cache(topo_info, cache->share_level) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
next prev parent reply other threads:[~2024-01-08 8:17 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-08 8:27 [PATCH v7 00/16] Support smp.clusters for x86 in QEMU Zhao Liu
2024-01-08 8:27 ` [PATCH v7 01/16] i386/cpu: Fix i/d-cache topology to core level for Intel CPU Zhao Liu
2024-01-08 8:27 ` [PATCH v7 02/16] i386/cpu: Use APIC ID offset to encode cache topo in CPUID[4] Zhao Liu
2024-01-10 9:31 ` Xiaoyao Li
2024-01-11 8:43 ` Zhao Liu
2024-01-14 14:11 ` Xiaoyao Li
2024-01-15 3:04 ` Zhao Liu
2024-01-15 3:51 ` Xiaoyao Li
2024-01-15 4:16 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 03/16] i386/cpu: Consolidate the use of topo_info in cpu_x86_cpuid() Zhao Liu
2024-01-10 11:52 ` Xiaoyao Li
2024-01-11 8:46 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 04/16] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB] Zhao Liu
2024-01-08 8:27 ` [PATCH v7 05/16] i386: Decouple CPUID[0x1F] subleaf with specific topology level Zhao Liu
2024-01-11 3:19 ` Xiaoyao Li
2024-01-11 9:07 ` Zhao Liu
2024-01-23 9:56 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 06/16] i386: Introduce module-level cpu topology to CPUX86State Zhao Liu
2024-01-08 8:27 ` [PATCH v7 07/16] i386: Support modules_per_die in X86CPUTopoInfo Zhao Liu
2024-01-11 5:53 ` Xiaoyao Li
2024-01-11 9:18 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 08/16] i386: Expose module level in CPUID[0x1F] Zhao Liu
2024-01-11 6:04 ` Xiaoyao Li
2024-01-11 9:21 ` Zhao Liu
2024-01-15 3:25 ` Yuan Yao
2024-01-15 4:09 ` Zhao Liu
2024-01-15 4:34 ` Xiaoyao Li
2024-01-15 5:20 ` Yuan Yao
2024-01-15 6:20 ` Zhao Liu
2024-01-15 6:57 ` Yuan Yao
2024-01-15 7:20 ` Zhao Liu
2024-01-15 9:03 ` Yuan Yao
2024-01-15 6:12 ` Zhao Liu
2024-01-15 6:11 ` Xiaoyao Li
2024-01-15 6:35 ` Zhao Liu
2024-01-15 7:16 ` Xiaoyao Li
2024-01-15 15:46 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 09/16] i386: Support module_id in X86CPUTopoIDs Zhao Liu
2024-01-14 12:42 ` Xiaoyao Li
2024-01-15 3:52 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 10/16] i386/cpu: Introduce cluster-id to X86CPU Zhao Liu
2024-01-14 13:49 ` Xiaoyao Li
2024-01-15 3:27 ` Zhao Liu
2024-01-15 4:18 ` Xiaoyao Li
2024-01-15 5:59 ` Zhao Liu
2024-01-15 7:45 ` Xiaoyao Li
2024-01-15 15:18 ` Zhao Liu
2024-01-16 16:40 ` Xiaoyao Li
2024-01-19 7:59 ` Zhao Liu
2024-01-26 3:37 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 11/16] tests: Add test case of APIC ID for module level parsing Zhao Liu
2024-01-08 8:27 ` [PATCH v7 12/16] hw/i386/pc: Support smp.clusters for x86 PC machine Zhao Liu
2024-01-08 8:27 ` [PATCH v7 13/16] i386: Add cache topology info in CPUCacheInfo Zhao Liu
2024-01-08 8:27 ` [PATCH v7 14/16] i386: Use CPUCacheInfo.share_level to encode CPUID[4] Zhao Liu
2024-01-14 14:31 ` Xiaoyao Li
2024-01-15 3:40 ` Zhao Liu
2024-01-15 4:25 ` Xiaoyao Li
2024-01-15 6:25 ` Zhao Liu
2024-01-15 7:00 ` Xiaoyao Li
2024-01-15 14:55 ` Zhao Liu
2024-01-08 8:27 ` [PATCH v7 15/16] i386: Use offsets get NumSharingCache for CPUID[0x8000001D].EAX[bits 25:14] Zhao Liu
2024-01-14 14:42 ` Xiaoyao Li
2024-01-15 3:48 ` Zhao Liu
2024-01-15 4:27 ` Xiaoyao Li
2024-01-15 14:54 ` Zhao Liu
2024-01-08 8:27 ` Zhao Liu [this message]
2024-01-08 17:46 ` [PATCH v7 00/16] Support smp.clusters for x86 in QEMU Moger, Babu
2024-01-09 1:48 ` Zhao Liu
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