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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id v27-20020a170906181b00b00a2ae0aa9002sm2004436eje.40.2024.01.10.03.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Jan 2024 03:37:36 -0800 (PST) Date: Wed, 10 Jan 2024 12:37:35 +0100 From: Andrew Jones To: Conor Dooley Cc: qemu-riscv@nongnu.org, Conor Dooley , Alistair Francis , Bin Meng , Palmer Dabbelt , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-devel@nongnu.org Subject: Re: [PATCH v3 1/2] target/riscv: use misa_mxl_max to populate isa string rather than TARGET_LONG_BITS Message-ID: <20240110-aa3945e12c7bb11eeb87edfc@orel> References: <20240110-mold-renovate-256db1b5c70e@spud> <20240110-eastward-sulfide-f365c89681e0@spud> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240110-eastward-sulfide-f365c89681e0@spud> Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jan 10, 2024 at 10:25:36AM +0000, Conor Dooley wrote: > From: Conor Dooley > > A cpu may not have the same xlen as the compile time target, and > misa_mxl_max is the source of truth for what the hart supports. > > Reported-by: Andrew Jones > Link: https://lore.kernel.org/qemu-riscv/20240108-efa3f83dcd3997dc0af458d7@orel/ > Signed-off-by: Conor Dooley > --- > Perhaps this misa_mxl_max -> width conversion should exist as a macro? > There's now 3 individual conversions of this type - two I added and one > in the gdb code. A macro is a good idea. I had to go look at Table 3.1 of the priv spec to understand the 16 shift stuff. > --- > target/riscv/cpu.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8cbfc7e781..5b5da970f2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1860,7 +1860,9 @@ char *riscv_isa_string(RISCVCPU *cpu) > int i; > const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); > char *isa_str = g_new(char, maxlen); > - char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); > + int xlen = 16 << cpu->env.misa_mxl_max; > + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen); > + > for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { > if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { > *p++ = qemu_tolower(riscv_single_letter_exts[i]); > -- > 2.39.2 > Reviewed-by: Andrew Jones