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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: philmd@linaro.org, pbonzini@redhat.com
Subject: [PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
Date: Thu, 11 Jan 2024 09:44:01 +1100	[thread overview]
Message-ID: <20240110224408.10444-32-richard.henderson@linaro.org> (raw)
In-Reply-To: <20240110224408.10444-1-richard.henderson@linaro.org>

Using cr0 means we could choose to use rc=1 to compute the condition.
Adjust the tables and tcg_out_cmp that feeds them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/ppc/tcg-target.c.inc | 68 ++++++++++++++++++++--------------------
 1 file changed, 34 insertions(+), 34 deletions(-)

diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 830d2fe73a..b9323baa86 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -671,30 +671,30 @@ enum {
 };
 
 static const uint32_t tcg_to_bc[] = {
-    [TCG_COND_EQ]  = BC | BI(7, CR_EQ) | BO_COND_TRUE,
-    [TCG_COND_NE]  = BC | BI(7, CR_EQ) | BO_COND_FALSE,
-    [TCG_COND_LT]  = BC | BI(7, CR_LT) | BO_COND_TRUE,
-    [TCG_COND_GE]  = BC | BI(7, CR_LT) | BO_COND_FALSE,
-    [TCG_COND_LE]  = BC | BI(7, CR_GT) | BO_COND_FALSE,
-    [TCG_COND_GT]  = BC | BI(7, CR_GT) | BO_COND_TRUE,
-    [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
-    [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
-    [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
-    [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
+    [TCG_COND_EQ]  = BC | BI(0, CR_EQ) | BO_COND_TRUE,
+    [TCG_COND_NE]  = BC | BI(0, CR_EQ) | BO_COND_FALSE,
+    [TCG_COND_LT]  = BC | BI(0, CR_LT) | BO_COND_TRUE,
+    [TCG_COND_GE]  = BC | BI(0, CR_LT) | BO_COND_FALSE,
+    [TCG_COND_LE]  = BC | BI(0, CR_GT) | BO_COND_FALSE,
+    [TCG_COND_GT]  = BC | BI(0, CR_GT) | BO_COND_TRUE,
+    [TCG_COND_LTU] = BC | BI(0, CR_LT) | BO_COND_TRUE,
+    [TCG_COND_GEU] = BC | BI(0, CR_LT) | BO_COND_FALSE,
+    [TCG_COND_LEU] = BC | BI(0, CR_GT) | BO_COND_FALSE,
+    [TCG_COND_GTU] = BC | BI(0, CR_GT) | BO_COND_TRUE,
 };
 
 /* The low bit here is set if the RA and RB fields must be inverted.  */
 static const uint32_t tcg_to_isel[] = {
-    [TCG_COND_EQ]  = ISEL | BC_(7, CR_EQ),
-    [TCG_COND_NE]  = ISEL | BC_(7, CR_EQ) | 1,
-    [TCG_COND_LT]  = ISEL | BC_(7, CR_LT),
-    [TCG_COND_GE]  = ISEL | BC_(7, CR_LT) | 1,
-    [TCG_COND_LE]  = ISEL | BC_(7, CR_GT) | 1,
-    [TCG_COND_GT]  = ISEL | BC_(7, CR_GT),
-    [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
-    [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
-    [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
-    [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
+    [TCG_COND_EQ]  = ISEL | BC_(0, CR_EQ),
+    [TCG_COND_NE]  = ISEL | BC_(0, CR_EQ) | 1,
+    [TCG_COND_LT]  = ISEL | BC_(0, CR_LT),
+    [TCG_COND_GE]  = ISEL | BC_(0, CR_LT) | 1,
+    [TCG_COND_LE]  = ISEL | BC_(0, CR_GT) | 1,
+    [TCG_COND_GT]  = ISEL | BC_(0, CR_GT),
+    [TCG_COND_LTU] = ISEL | BC_(0, CR_LT),
+    [TCG_COND_GEU] = ISEL | BC_(0, CR_LT) | 1,
+    [TCG_COND_LEU] = ISEL | BC_(0, CR_GT) | 1,
+    [TCG_COND_GTU] = ISEL | BC_(0, CR_GT),
 };
 
 static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
@@ -1827,7 +1827,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
     if (have_isa_3_10) {
         tcg_insn_unit bi, opc;
 
-        tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+        tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type);
 
         /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */
         bi = tcg_to_bc[cond] & (0x1f << 16);
@@ -1880,7 +1880,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
     if (have_isel) {
         int isel, tab;
 
-        tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+        tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type);
 
         isel = tcg_to_isel[cond];
 
@@ -1966,7 +1966,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond,
                            TCGArg arg1, TCGArg arg2, int const_arg2,
                            TCGLabel *l, TCGType type)
 {
-    tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+    tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type);
     tcg_out_bc_lab(s, cond, l);
 }
 
@@ -1980,7 +1980,7 @@ static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
         return;
     }
 
-    tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
+    tcg_out_cmp(s, cond, c1, c2, const_c2, 0, type);
 
     if (have_isel) {
         int isel = tcg_to_isel[cond];
@@ -2024,7 +2024,7 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
     if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) {
         tcg_out32(s, opc | RA(a0) | RS(a1));
     } else {
-        tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type);
+        tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 0, type);
         /* Note that the only other valid constant for a2 is 0.  */
         if (have_isel) {
             tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1));
@@ -2079,7 +2079,7 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
     do_equality:
         tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
         tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
-        tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
+        tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
         break;
 
     case TCG_COND_LT:
@@ -2097,8 +2097,8 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
 
         tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
         tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
-        tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
-        tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
+        tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
+        tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ));
         break;
 
     default:
@@ -2110,8 +2110,8 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
                              const int *const_args)
 {
     tcg_out_cmp2(s, args + 1, const_args + 1);
-    tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
-    tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
+    tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0));
+    tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31);
 }
 
 static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
@@ -2442,12 +2442,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
             tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2,
                         0, 6, TCG_TYPE_I32);
 
-            /* Combine comparisons into cr7. */
-            tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
+            /* Combine comparisons into cr0. */
+            tcg_out32(s, CRAND | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
         } else {
-            /* Full comparison into cr7. */
+            /* Full comparison into cr0. */
             tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2,
-                        0, 7, addr_type);
+                        0, 0, addr_type);
         }
 
         /* Load a pointer into the current opcode w/conditional branch-link. */
-- 
2.34.1



  parent reply	other threads:[~2024-01-10 22:47 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-10 22:43 [PATCH v3 00/38] tcg: Introduce TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 01/38] " Richard Henderson
2024-01-10 22:43 ` [PATCH v3 02/38] tcg: Introduce TCG_TARGET_HAS_tst Richard Henderson
2024-01-16 21:42   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 03/38] tcg/optimize: Split out arg_is_const_val Richard Henderson
2024-01-10 22:43 ` [PATCH v3 04/38] tcg/optimize: Split out do_constant_folding_cond1 Richard Henderson
2024-01-10 22:43 ` [PATCH v3 05/38] tcg/optimize: Do swap_commutative2 in do_constant_folding_cond2 Richard Henderson
2024-01-10 22:43 ` [PATCH v3 06/38] tcg/optimize: Handle TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ, NE} if unsupported Richard Henderson
2024-01-16 22:02   ` [PATCH v3 07/38] tcg/optimize: Lower TCG_COND_TST{EQ,NE} " Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 08/38] target/alpha: Pass immediate value to gen_bcond_internal() Richard Henderson
2024-01-16 22:02   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 09/38] target/alpha: Use TCG_COND_TST{EQ,NE} for BLB{C,S} Richard Henderson
2024-01-16 22:03   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 10/38] target/alpha: Use TCG_COND_TST{EQ, NE} for CMOVLB{C, S} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 11/38] target/alpha: Use TCG_COND_TSTNE for gen_fold_mzero Richard Henderson
2024-01-10 22:43 ` [PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ, NE} in gen_fcc_cond Richard Henderson
2024-01-16 22:06   ` [PATCH v3 12/38] target/m68k: Use TCG_COND_TST{EQ,NE} " Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 13/38] target/sparc: Use TCG_COND_TSTEQ in gen_op_mulscc Richard Henderson
2024-01-16 21:44   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 14/38] target/s390x: Use TCG_COND_TSTNE for CC_OP_{TM,ICM} Richard Henderson
2024-01-19 21:59   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 15/38] target/s390x: Improve general case of disas_jcc Richard Henderson
2024-01-16 22:19   ` Philippe Mathieu-Daudé
2024-01-17  3:19     ` Richard Henderson
2024-01-19 23:27       ` Philippe Mathieu-Daudé
2024-01-19 23:22   ` [PATCH v3 15/38 1/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (1/5) Philippe Mathieu-Daudé
2024-01-19 23:22   ` [PATCH v3 15/38 2/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (2/5) Philippe Mathieu-Daudé
2024-01-19 23:22   ` [PATCH v3 15/38 3/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (3/5) Philippe Mathieu-Daudé
2024-01-19 23:23   ` [PATCH v3 15/38 4/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (4/5) Philippe Mathieu-Daudé
2024-01-19 23:23   ` [PATCH v3 15/38 5/6] target/s390x: Reorder CC_OP_STATIC switch case in disas_jcc (5/5) Philippe Mathieu-Daudé
2024-01-19 23:23   ` [PATCH v3 15/38 6/6] target/s390x: Improve general case of disas_jcc Philippe Mathieu-Daudé
2024-01-19 23:27     ` Philippe Mathieu-Daudé
2024-01-22 21:38     ` Ilya Leoshkevich
2024-01-10 22:43 ` [PATCH v3 16/38] tcg: Add TCGConst argument to tcg_target_const_match Richard Henderson
2024-01-10 22:43 ` [PATCH v3 17/38] tcg/aarch64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-19 22:09   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 18/38] tcg/aarch64: Generate TBZ, TBNZ Richard Henderson
2024-01-19 22:47   ` [PATCH v3 18/38 1/2] tcg/aarch64: Massage tcg_out_brcond() Philippe Mathieu-Daudé
2024-01-19 22:47   ` [PATCH v3 18/38 2/2] tcg/aarch64: Generate TBZ, TBNZ Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 19/38] tcg/aarch64: Generate CBNZ for TSTNE of UINT32_MAX Richard Henderson
2024-01-22 14:20   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 20/38] tcg/arm: Factor tcg_out_cmp() out Richard Henderson
2024-01-16 22:22   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 21/38] tcg/arm: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-16 22:26   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 22/38] tcg/i386: Pass x86 condition codes to tcg_out_cmov Richard Henderson
2024-01-10 22:43 ` [PATCH v3 23/38] tcg/i386: Move tcg_cond_to_jcc[] into tcg_out_cmp Richard Henderson
2024-01-10 22:43 ` [PATCH v3 24/38] tcg/i386: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:43 ` [PATCH v3 25/38] tcg/i386: Improve TSTNE/TESTEQ vs powers of two Richard Henderson
2024-01-10 22:43 ` [PATCH v3 26/38] tcg/i386: Use TEST r,r to test 8/16/32 bits Richard Henderson
2024-01-20 11:02   ` Philippe Mathieu-Daudé
2024-01-10 22:43 ` [PATCH v3 27/38] tcg/sparc64: Hoist read of tcg_cond_to_rcond Richard Henderson
2024-01-10 22:43 ` [PATCH v3 28/38] tcg/sparc64: Pass TCGCond to tcg_out_cmp Richard Henderson
2024-01-10 22:43 ` [PATCH v3 29/38] tcg/sparc64: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-10 22:44 ` [PATCH v3 30/38] tcg/ppc: Sink tcg_to_bc usage into tcg_out_bc Richard Henderson
2024-01-10 22:44 ` Richard Henderson [this message]
2024-01-16 21:51   ` [PATCH v3 31/38] tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 32/38] tcg/ppc: Tidy up tcg_target_const_match Richard Henderson
2024-01-10 22:44 ` [PATCH v3 33/38] tcg/ppc: Add TCG_CT_CONST_CMP Richard Henderson
2024-01-19 22:12   ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 34/38] tcg/ppc: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-19 22:20   ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 35/38] tcg/s390x: Split constraint A into J+U Richard Henderson
2024-01-16 21:55   ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 36/38] tcg/s390x: Add TCG_CT_CONST_CMP Richard Henderson
2024-01-16 21:57   ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 37/38] tcg/s390x: Support TCG_COND_TST{EQ,NE} Richard Henderson
2024-01-23  5:36   ` Philippe Mathieu-Daudé
2024-01-10 22:44 ` [PATCH v3 38/38] tcg/tci: " Richard Henderson

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