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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id g17-20020a170906395100b00a2c29fe8b2esm547522eje.212.2024.01.11.05.02.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 05:02:04 -0800 (PST) Date: Thu, 11 Jan 2024 14:02:03 +0100 From: Andrew Jones To: Daniel Henrique Barboza Cc: Rob Bradford , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com Subject: Re: Re: [PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type Message-ID: <20240111-558c99b8f3be4297e9ae4118@orel> References: <20240109171848.32237-1-rbradford@rivosinc.com> <20240109171848.32237-4-rbradford@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza wrote: > > > On 1/9/24 14:07, Rob Bradford wrote: > > Signed-off-by: Rob Bradford > > --- > > target/riscv/tcg/tcg-cpu.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > > index f10871d352..9705daec93 100644 > > --- a/target/riscv/tcg/tcg-cpu.c > > +++ b/target/riscv/tcg/tcg-cpu.c > > @@ -999,7 +999,8 @@ static void riscv_init_max_cpu_extensions(Object *obj) > > const RISCVCPUMultiExtConfig *prop; > > /* Enable RVG, RVJ and RVV that are disabled by default */ > > - riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); > > + riscv_cpu_set_misa(env, env->misa_mxl, > > + env->misa_ext | RVG | RVJ | RVV | RVB); > > I'm aware that we decided a while ago the 'max' CPU could only have non-vendor and > non-experimental extensions enabled. RVB is experimental, so in theory we shouldn't > enable it. > > But RVB is an alias for zba, zbb and zbs, extensions that the 'max' CPU is already > enabling. In this case I think it's sensible to enable RVB here since it would just > reflect stuff that it's already happening. It's also setting the B bit in misa, which, until this spec is at least frozen, is a reserved bit and reserved bits "must return zero when read". I don't want to stand in the way of progress and it seems 99.9% likely that the spec will be frozen and ratified, but, if we want to stick to our policies (which we should document), then even the 'max' cpu type should require x-b be added to the command line if it wants the B bit set in misa. Thanks, drew