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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id ew3-20020a056402538300b00558a1937dddsm469808edb.63.2024.01.11.05.09.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 05:09:32 -0800 (PST) Date: Thu, 11 Jan 2024 14:09:31 +0100 From: Andrew Jones To: Rob Bradford Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com Subject: Re: [PATCH 2/3] target/riscv: Add step to validate 'B' extension Message-ID: <20240111-cbafb19054363e2e33dbd317@orel> References: <20240109171848.32237-1-rbradford@rivosinc.com> <20240109171848.32237-3-rbradford@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240109171848.32237-3-rbradford@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Jan 09, 2024 at 05:07:36PM +0000, Rob Bradford wrote: > If the B extension is enabled warn if the user has disabled any of the > required extensions that are part of the 'B' extension. Conversely > enable the extensions that make up the 'B' extension if it is enabled. > > Signed-off-by: Rob Bradford > --- > target/riscv/tcg/tcg-cpu.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index fda54671d5..f10871d352 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -273,6 +273,35 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > } > } > > +static void riscv_cpu_validate_b(RISCVCPU *cpu) > +{ > + const char *warn_msg = "RVB mandates disabled extension %s"; > + > + if (!cpu->cfg.ext_zba) { > + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zba))) { > + cpu->cfg.ext_zba = true; > + } else { > + warn_report(warn_msg, "zba"); > + } > + } > + > + if (!cpu->cfg.ext_zbb) { > + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbb))) { > + cpu->cfg.ext_zbb = true; > + } else { > + warn_report(warn_msg, "zbb"); > + } > + } > + > + if (!cpu->cfg.ext_zbs) { > + if (!cpu_cfg_ext_is_user_set(CPU_CFG_OFFSET(ext_zbs))) { > + cpu->cfg.ext_zbs = true; > + } else { > + warn_report(warn_msg, "zbs"); > + } > + } > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > @@ -309,6 +338,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; > } > > + if (riscv_has_ext(env, RVB)) { > + riscv_cpu_validate_b(cpu); > + } > + > if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { > error_setg(errp, > "I and E extensions are incompatible"); > -- > 2.43.0 > > Reviewed-by: Andrew Jones