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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id f11-20020a170906084b00b00a2c32b6053dsm564860ejd.166.2024.01.11.05.14.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 Jan 2024 05:14:58 -0800 (PST) Date: Thu, 11 Jan 2024 14:14:57 +0100 From: Andrew Jones To: Rob Bradford Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com Subject: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension Message-ID: <20240111-df7a6acf3109b630469591a1@orel> References: <20240109171848.32237-1-rbradford@rivosinc.com> <20240109171848.32237-2-rbradford@rivosinc.com> <20240111-585fe1291fcaa1e0432674e3@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240111-585fe1291fcaa1e0432674e3@orel> Received-SPF: pass client-ip=2a00:1450:4864:20::136; envelope-from=ajones@ventanamicro.com; helo=mail-lf1-x136.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote: > On Tue, Jan 09, 2024 at 05:07:35PM +0000, Rob Bradford wrote: > > Add the infrastructure for the 'B' extension which is the union of the > > Zba, Zbb and Zbs instructions. > > > > Signed-off-by: Rob Bradford > > --- > > target/riscv/cpu.c | 5 +++-- > > target/riscv/cpu.h | 1 + > > target/riscv/tcg/tcg-cpu.c | 1 + > > 3 files changed, 5 insertions(+), 2 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index b07a76ef6b..22f8e527ff 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -38,9 +38,9 @@ > > #include "tcg/tcg.h" > > > > /* RISC-V CPU definitions */ > > -static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > > +static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH"; > > Is there a corresponding proposed change to table 29.1 of the nonpriv spec > which states B comes after C and before P? If so, can you provide a link > to it? Otherwise, how do we know that? Oh, I see. The unpriv spec B chapter comes after the C chapter (and before J, P, ...). I still wonder if we'll have a 29.1 table update with the ratification of this extension though. Thanks, drew