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[176.184.43.236]) by smtp.gmail.com with ESMTPSA id z11-20020a5d44cb000000b00336898daceasm1048278wrr.96.2024.01.11.04.02.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 11 Jan 2024 04:02:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Weiwei Li , Alistair Francis , qemu-s390x@nongnu.org, Michael Tokarev , David Hildenbrand , Christian Borntraeger , qemu-riscv@nongnu.org, Palmer Dabbelt , Bin Meng , qemu-trivial@nongnu.org, Halil Pasic , Paolo Bonzini , Ilya Leoshkevich , Eduardo Habkost , Laurent Vivier , Liu Zhiwei , Eric Farman , Thomas Huth , Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 5/5] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' Date: Thu, 11 Jan 2024 13:02:21 +0100 Message-ID: <20240111120221.35072-6-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20240111120221.35072-1-philmd@linaro.org> References: <20240111120221.35072-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The tcg_cpu_FOO() names are riscv specific, so rename them as riscv_tcg_cpu_FOO() (as other names in this file) to ease navigating the code. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 14133ff665..994ca1cdf9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -929,7 +929,7 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj) * -> cpu_exec_realizefn() * -> tcg_cpu_realize() (via accel_cpu_common_realize()) */ -static bool tcg_cpu_realize(CPUState *cs, Error **errp) +static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) { RISCVCPU *cpu = RISCV_CPU(cs); Error *local_err = NULL; @@ -1372,7 +1372,7 @@ static bool riscv_cpu_has_max_extensions(Object *cpu_obj) return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; } -static void tcg_cpu_instance_init(CPUState *cs) +static void riscv_tcg_cpu_instance_init(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); Object *obj = OBJECT(cpu); @@ -1386,7 +1386,7 @@ static void tcg_cpu_instance_init(CPUState *cs) } } -static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) +static void riscv_tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) { /* * All cpus use the same set of operations. @@ -1394,30 +1394,30 @@ static void tcg_cpu_init_ops(AccelCPUClass *accel_cpu, CPUClass *cc) cc->tcg_ops = &riscv_tcg_ops; } -static void tcg_cpu_class_init(CPUClass *cc) +static void riscv_tcg_cpu_class_init(CPUClass *cc) { - cc->init_accel_cpu = tcg_cpu_init_ops; + cc->init_accel_cpu = riscv_tcg_cpu_init_ops; } -static void tcg_cpu_accel_class_init(ObjectClass *oc, void *data) +static void riscv_tcg_cpu_accel_class_init(ObjectClass *oc, void *data) { AccelCPUClass *acc = ACCEL_CPU_CLASS(oc); - acc->cpu_class_init = tcg_cpu_class_init; - acc->cpu_instance_init = tcg_cpu_instance_init; - acc->cpu_target_realize = tcg_cpu_realize; + acc->cpu_class_init = riscv_tcg_cpu_class_init; + acc->cpu_instance_init = riscv_tcg_cpu_instance_init; + acc->cpu_target_realize = riscv_tcg_cpu_realize; } -static const TypeInfo tcg_cpu_accel_type_info = { +static const TypeInfo riscv_tcg_cpu_accel_type_info = { .name = ACCEL_CPU_NAME("tcg"), .parent = TYPE_ACCEL_CPU, - .class_init = tcg_cpu_accel_class_init, + .class_init = riscv_tcg_cpu_accel_class_init, .abstract = true, }; -static void tcg_cpu_accel_register_types(void) +static void riscv_tcg_cpu_accel_register_types(void) { - type_register_static(&tcg_cpu_accel_type_info); + type_register_static(&riscv_tcg_cpu_accel_type_info); } -type_init(tcg_cpu_accel_register_types); +type_init(riscv_tcg_cpu_accel_register_types); -- 2.41.0