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Tsirkin" To: Bernhard Beschow Cc: qemu-devel@nongnu.org, Eduardo Habkost , Richard Henderson , Paolo Bonzini , Marcel Apfelbaum Subject: Re: [PATCH v2 0/3] Fix PIC interrupt handling of x86 CPUs if APIC is globally disabled Message-ID: <20240114055534-mutt-send-email-mst@kernel.org> References: <20240106132546.21248-1-shentey@gmail.com> <2744F3E2-D8F5-42F1-8520-7FE8C202C341@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2744F3E2-D8F5-42F1-8520-7FE8C202C341@gmail.com> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -48 X-Spam_score: -4.9 X-Spam_bar: ---- X-Spam_report: (-4.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.758, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Sun, Jan 14, 2024 at 10:52:28AM +0000, Bernhard Beschow wrote: > > > Am 6. Januar 2024 13:25:43 UTC schrieb Bernhard Beschow : > >This series is part of my work emulating the VIA Apollo Pro 133T chipset in QEMU > > > >[1] and testing it by running real-world BIOSes on it. The first two patches fix > > > >an issue regarding PIC interrupt handling, the third one just fixes a typo in a > > > >comment. > > > > > > > >During testing, I've found that the boot process gets stuck for some BIOSes that > > > >disable the LAPIC globally (by disabling the enable bit in the base address > > > >register). QEMU seems to emulate PIC interrupt handling only if a CPU doesn't > > > >have a LAPIC, and always emulates LAPIC interrupt handling if one is present. > > > >According to the Intel documentation, a CPU should resort to PIC interrupt > > > >handling if its LAPIC is globally didabled. This series fixes this corner case > > > >which makes the boot process succeed. More details can be found in the commit > > > >message. > > > > > > > >Testing done: > > > >* `make check` > > > >* `make check-avocado` > > > > > > > >v2: > > > >* Pick up R-b tag > > > >* Split and rework interrupt handling patch to consider i486 SMP systems. This > > > > required dropping Alex' R-b tag. > > > > Ping Tagged now. Thanks! > > > > > >[1] https://github.com/shentok/qemu/tree/via-apollo-pro-133t > > > > > > > >Bernhard Beschow (3): > > > > hw/i386/x86: Reverse if statement > > > > hw/i386/x86: Fix PIC interrupt handling if APIC is globally disabled > > > > target/i386/cpu: Fix typo in comment > > > > > > > > include/hw/i386/apic.h | 1 + > > > > hw/i386/x86.c | 8 ++++---- > > > > hw/intc/apic_common.c | 13 +++++++++++++ > > > > target/i386/cpu.c | 2 +- > > > > 4 files changed, 19 insertions(+), 5 deletions(-) > > > > > > > >-- > > >2.43.0 > > > > > >