* [PATCH v9 0/4] gdbstub and TCG plugin improvements
@ 2024-01-15 6:31 Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 1/4] hw/riscv: Use misa_mxl instead of misa_mxl_max Akihiko Odaki
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Akihiko Odaki @ 2024-01-15 6:31 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
This series extracts fixes and refactorings that can be applied
independently from "[PATCH v9 00/23] plugins: Allow to read registers".
The patch "target/riscv: Move MISA limits to class" was replaced with
patch "target/riscv: Move misa_mxl_max to class" since I found instances
may have different misa_ext_mask.
V6 -> V7:
Rebased.
V5 -> V6:
Added patch "default-configs: Add TARGET_XML_FILES definition".
Rebased.
V4 -> V5:
Added patch "hw/riscv: Use misa_mxl instead of misa_mxl_max".
V3 -> V4:
Added patch "gdbstub: Check if gdb_regs is NULL".
V2 -> V3:
Restored patch sets from the previous version.
Rebased to commit 800485762e6564e04e2ab315132d477069562d91.
V1 -> V2:
Added patch "target/riscv: Do not allow MXL_RV32 for TARGET_RISCV64".
Added patch "target/riscv: Initialize gdb_core_xml_file only once".
Dropped patch "target/riscv: Remove misa_mxl validation".
Dropped patch "target/riscv: Move misa_mxl_max to class".
Dropped patch "target/riscv: Validate misa_mxl_max only once".
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
Changes in v9:
- Rebased to commit 977542ded7e6b28d2bc077bcda24568c716e393c.
- Link to v8: https://lore.kernel.org/r/20231218-riscv-v8-0-c9bf2b1582d7@daynix.com
Changes in v8:
- Added a more detailed explanation for patch "hw/riscv: Use misa_mxl
instead of misa_mxl_max". (Alistair Francis)
- Link to v7: https://lore.kernel.org/r/20231213-riscv-v7-0-a760156a337f@daynix.com
---
Akihiko Odaki (4):
hw/riscv: Use misa_mxl instead of misa_mxl_max
target/riscv: Remove misa_mxl validation
target/riscv: Move misa_mxl_max to class
target/riscv: Validate misa_mxl_max only once
target/riscv/cpu.h | 4 +-
hw/riscv/boot.c | 2 +-
target/riscv/cpu.c | 183 ++++++++++++++++++++++++++-------------------
target/riscv/gdbstub.c | 12 ++-
target/riscv/kvm/kvm-cpu.c | 10 +--
target/riscv/machine.c | 7 +-
target/riscv/tcg/tcg-cpu.c | 44 ++---------
target/riscv/translate.c | 3 +-
8 files changed, 134 insertions(+), 131 deletions(-)
---
base-commit: 977542ded7e6b28d2bc077bcda24568c716e393c
change-id: 20231213-riscv-fcc9640986cf
Best regards,
--
Akihiko Odaki <akihiko.odaki@daynix.com>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v9 1/4] hw/riscv: Use misa_mxl instead of misa_mxl_max
2024-01-15 6:31 [PATCH v9 0/4] gdbstub and TCG plugin improvements Akihiko Odaki
@ 2024-01-15 6:31 ` Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 2/4] target/riscv: Remove misa_mxl validation Akihiko Odaki
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Akihiko Odaki @ 2024-01-15 6:31 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
A later commit requires one extra step to retrieve misa_mxl_max. As
misa_mxl is semantically more correct and does not need such a extra
step, refer to misa_mxl instead. Below is the explanation why misa_mxl
is more semantically correct to refer to than misa_mxl_max in this case.
Currently misa_mxl always equals to misa_mxl_max so it does not matter
which of misa_mxl or misa_mxl_max to refer to. However, it is possible
to have different values for misa_mxl and misa_mxl_max if QEMU gains a
new feature to load a RV32 kernel on a RV64 system, for example. For
such a behavior, the real system will need the firmware to switch MXL to
RV32, and if QEMU implements the same behavior, mxl will represent the
MXL that corresponds to the kernel being loaded. Therefore, it is more
appropriate to refer to mxl instead of misa_mxl_max when
misa_mxl != misa_mxl_max.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
---
hw/riscv/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 0ffca05189f0..bc67c0bd1890 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -36,7 +36,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
- return harts->harts[0].env.misa_mxl_max == MXL_RV32;
+ return harts->harts[0].env.misa_mxl == MXL_RV32;
}
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 2/4] target/riscv: Remove misa_mxl validation
2024-01-15 6:31 [PATCH v9 0/4] gdbstub and TCG plugin improvements Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 1/4] hw/riscv: Use misa_mxl instead of misa_mxl_max Akihiko Odaki
@ 2024-01-15 6:31 ` Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 3/4] target/riscv: Move misa_mxl_max to class Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 4/4] target/riscv: Validate misa_mxl_max only once Akihiko Odaki
3 siblings, 0 replies; 5+ messages in thread
From: Akihiko Odaki @ 2024-01-15 6:31 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
It is initialized with a simple assignment and there is little room for
error. In fact, the validation is even more complex.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/tcg/tcg-cpu.c | 15 +++------------
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 14133ff66568..b85b0d036a61 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -268,7 +268,7 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
}
}
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
+static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPUClass *cc = CPU_CLASS(mcc);
@@ -288,11 +288,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
default:
g_assert_not_reached();
}
-
- if (env->misa_mxl_max != env->misa_mxl) {
- error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
- return;
- }
}
static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
@@ -932,7 +927,6 @@ static bool riscv_cpu_is_vendor(Object *cpu_obj)
static bool tcg_cpu_realize(CPUState *cs, Error **errp)
{
RISCVCPU *cpu = RISCV_CPU(cs);
- Error *local_err = NULL;
if (!riscv_cpu_tcg_compatible(cpu)) {
g_autofree char *name = riscv_cpu_get_name(cpu);
@@ -941,14 +935,11 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
- riscv_cpu_validate_misa_mxl(cpu, &local_err);
- if (local_err != NULL) {
- error_propagate(errp, local_err);
- return false;
- }
+ riscv_cpu_validate_misa_mxl(cpu);
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
+ Error *local_err = NULL;
CPU(cs)->tcg_cflags |= CF_PCREL;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 3/4] target/riscv: Move misa_mxl_max to class
2024-01-15 6:31 [PATCH v9 0/4] gdbstub and TCG plugin improvements Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 1/4] hw/riscv: Use misa_mxl instead of misa_mxl_max Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 2/4] target/riscv: Remove misa_mxl validation Akihiko Odaki
@ 2024-01-15 6:31 ` Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 4/4] target/riscv: Validate misa_mxl_max only once Akihiko Odaki
3 siblings, 0 replies; 5+ messages in thread
From: Akihiko Odaki @ 2024-01-15 6:31 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
misa_mxl_max is common for all instances of a RISC-V CPU class so they
are better put into class.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 +-
target/riscv/cpu.c | 162 ++++++++++++++++++++++++---------------------
target/riscv/gdbstub.c | 12 ++--
target/riscv/kvm/kvm-cpu.c | 10 +--
target/riscv/machine.c | 7 +-
target/riscv/tcg/tcg-cpu.c | 12 ++--
target/riscv/translate.c | 3 +-
7 files changed, 112 insertions(+), 98 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5f3955c38db4..d269d53e59c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -185,7 +185,6 @@ struct CPUArchState {
/* RISCVMXL, but uint32_t for vmstate migration */
uint32_t misa_mxl; /* current mxl */
- uint32_t misa_mxl_max; /* max mxl for this cpu */
uint32_t misa_ext; /* current extensions */
uint32_t misa_ext_mask; /* max ext for this cpu */
uint32_t xl; /* current xlen */
@@ -466,6 +465,7 @@ struct RISCVCPUClass {
DeviceRealize parent_realize;
ResettablePhases parent_phases;
+ uint32_t misa_mxl_max; /* max mxl for this cpu */
};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
@@ -771,7 +771,7 @@ enum riscv_pmu_event_idx {
/* used by tcg/tcg-cpu.c*/
void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en);
bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset);
-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext);
+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext);
typedef struct RISCVCPUMultiExtConfig {
const char *name;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8cbfc7e781ad..4b742901e76e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -281,9 +281,8 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
}
}
-void riscv_cpu_set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
+void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
{
- env->misa_mxl_max = env->misa_mxl = mxl;
env->misa_ext_mask = env->misa_ext = ext;
}
@@ -396,11 +395,7 @@ static void riscv_any_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
-#if defined(TARGET_RISCV32)
- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-#elif defined(TARGET_RISCV64)
- riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
-#endif
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj),
@@ -421,16 +416,14 @@ static void riscv_max_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- RISCVMXL mlx = MXL_RV64;
-#ifdef TARGET_RISCV32
- mlx = MXL_RV32;
-#endif
- riscv_cpu_set_misa(env, mlx, 0);
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
- set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ?
- VM_1_10_SV32 : VM_1_10_SV57);
+#ifdef TARGET_RISCV32
+ set_satp_mode_max_supported(cpu, VM_1_10_SV32);
+#else
+ set_satp_mode_max_supported(cpu, VM_1_10_SV57);
+#endif
#endif
}
@@ -438,8 +431,6 @@ static void riscv_max_cpu_init(Object *obj)
static void rv64_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- riscv_cpu_set_misa(env, MXL_RV64, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -451,8 +442,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- riscv_cpu_set_misa(env, MXL_RV64,
- RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
@@ -470,7 +460,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -487,7 +477,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_11_0;
cpu->cfg.ext_zfa = true;
@@ -518,7 +508,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
+ riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
env->priv_ver = PRIV_VERSION_1_12_0;
/* Enable ISA extensions */
@@ -562,8 +552,6 @@ static void rv128_base_cpu_init(Object *obj)
exit(EXIT_FAILURE);
}
CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- riscv_cpu_set_misa(env, MXL_RV128, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -574,7 +562,7 @@ static void rv128_base_cpu_init(Object *obj)
static void rv64i_bare_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- riscv_cpu_set_misa(env, MXL_RV64, RVI);
+ riscv_cpu_set_misa_ext(env, RVI);
/* Remove the defaults from the parent class */
RISCV_CPU(obj)->cfg.ext_zicntr = false;
@@ -596,8 +584,6 @@ static void rv64i_bare_cpu_init(Object *obj)
static void rv32_base_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- /* We set this in the realise function */
- riscv_cpu_set_misa(env, MXL_RV32, 0);
/* Set latest version of privileged specification */
env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
@@ -609,8 +595,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env;
- riscv_cpu_set_misa(env, MXL_RV32,
- RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
@@ -628,7 +613,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -645,7 +630,7 @@ static void rv32_ibex_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_12_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -662,7 +647,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
CPURISCVState *env = &RISCV_CPU(obj)->env;
RISCVCPU *cpu = RISCV_CPU(obj);
- riscv_cpu_set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
+ riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
env->priv_ver = PRIV_VERSION_1_10_0;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -882,7 +867,7 @@ static void riscv_cpu_reset_hold(Object *obj)
mcc->parent_phases.hold(obj);
}
#ifndef CONFIG_USER_ONLY
- env->misa_mxl = env->misa_mxl_max;
+ env->misa_mxl = mcc->misa_mxl_max;
env->priv = PRV_M;
env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
if (env->misa_mxl > MXL_RV32) {
@@ -1258,6 +1243,12 @@ static void riscv_cpu_post_init(Object *obj)
static void riscv_cpu_init(Object *obj)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ CPURISCVState *env = &cpu->env;
+
+ env->misa_mxl = mcc->misa_mxl_max;
+
#ifndef CONFIG_USER_ONLY
qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
@@ -1795,7 +1786,7 @@ static void cpu_get_marchid(Object *obj, Visitor *v, const char *name,
visit_type_uint64(v, name, &value, errp);
}
-static void riscv_cpu_class_init(ObjectClass *c, void *data)
+static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
@@ -1837,6 +1828,13 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
device_class_set_props(dc, riscv_cpu_properties);
}
+static void riscv_cpu_class_init(ObjectClass *c, void *data)
+{
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
+
+ mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+}
+
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
int max_str_len)
{
@@ -1873,39 +1871,49 @@ char *riscv_isa_string(RISCVCPU *cpu)
return isa_str;
}
-#define DEFINE_CPU(type_name, initfn) \
- { \
- .name = type_name, \
- .parent = TYPE_RISCV_CPU, \
- .instance_init = initfn \
+#define DEFINE_CPU(type_name, misa_mxl_max, initfn) \
+ { \
+ .name = (type_name), \
+ .parent = TYPE_RISCV_CPU, \
+ .instance_init = (initfn), \
+ .class_init = riscv_cpu_class_init, \
+ .class_data = (void *)(misa_mxl_max) \
}
-#define DEFINE_DYNAMIC_CPU(type_name, initfn) \
- { \
- .name = type_name, \
- .parent = TYPE_RISCV_DYNAMIC_CPU, \
- .instance_init = initfn \
+#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
+ { \
+ .name = (type_name), \
+ .parent = TYPE_RISCV_DYNAMIC_CPU, \
+ .instance_init = (initfn), \
+ .class_init = riscv_cpu_class_init, \
+ .class_data = (void *)(misa_mxl_max) \
}
-#define DEFINE_VENDOR_CPU(type_name, initfn) \
- { \
- .name = type_name, \
- .parent = TYPE_RISCV_VENDOR_CPU, \
- .instance_init = initfn \
+#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \
+ { \
+ .name = (type_name), \
+ .parent = TYPE_RISCV_VENDOR_CPU, \
+ .instance_init = (initfn), \
+ .class_init = riscv_cpu_class_init, \
+ .class_data = (void *)(misa_mxl_max) \
}
-#define DEFINE_BARE_CPU(type_name, initfn) \
- { \
- .name = type_name, \
- .parent = TYPE_RISCV_BARE_CPU, \
- .instance_init = initfn \
+#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \
+ { \
+ .name = (type_name), \
+ .parent = TYPE_RISCV_BARE_CPU, \
+ .instance_init = (initfn), \
+ .class_init = riscv_cpu_class_init, \
+ .class_data = (void *)(misa_mxl_max) \
}
-#define DEFINE_PROFILE_CPU(type_name, initfn) \
- { \
- .name = type_name, \
- .parent = TYPE_RISCV_BARE_CPU, \
- .instance_init = initfn \
+#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
+ { \
+ .name = (type_name), \
+ .parent = TYPE_RISCV_BARE_CPU, \
+ .instance_init = (initfn), \
+ .class_init = riscv_cpu_class_init, \
+ .class_data = (void *)(misa_mxl_max) \
}
static const TypeInfo riscv_cpu_type_infos[] = {
@@ -1918,7 +1926,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.instance_post_init = riscv_cpu_post_init,
.abstract = true,
.class_size = sizeof(RISCVCPUClass),
- .class_init = riscv_cpu_class_init,
+ .class_init = riscv_cpu_common_class_init,
},
{
.name = TYPE_RISCV_DYNAMIC_CPU,
@@ -1935,25 +1943,27 @@ static const TypeInfo riscv_cpu_type_infos[] = {
.parent = TYPE_RISCV_CPU,
.abstract = true,
},
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init),
#if defined(TARGET_RISCV32)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32, riscv_any_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32, riscv_max_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32, rv32_base_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32, rv32_ibex_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32, rv32_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32, rv32_imafcu_nommu_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init),
- DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init),
- DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init),
- DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, rv64i_bare_cpu_init),
- DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, rva22u64_profile_cpu_init),
- DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, rva22s64_profile_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64, riscv_any_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64, riscv_max_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64, rv64_base_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64, rv64_sifive_e_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init),
+ DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init),
+ DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init),
+ DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I, MXL_RV64, rv64i_bare_cpu_init),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64, MXL_RV64, rva22u64_profile_cpu_init),
+ DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64, MXL_RV64, rva22s64_profile_cpu_init),
#endif
};
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 58b3ace0fe92..365040228a12 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -49,6 +49,7 @@ static const struct TypeSize vec_lanes[] = {
int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
target_ulong tmp;
@@ -61,7 +62,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
return 0;
}
- switch (env->misa_mxl_max) {
+ switch (mcc->misa_mxl_max) {
case MXL_RV32:
return gdb_get_reg32(mem_buf, tmp);
case MXL_RV64:
@@ -75,12 +76,13 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
int length = 0;
target_ulong tmp;
- switch (env->misa_mxl_max) {
+ switch (mcc->misa_mxl_max) {
case MXL_RV32:
tmp = (int32_t)ldl_p(mem_buf);
length = 4;
@@ -214,11 +216,12 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)
static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
GString *s = g_string_new(NULL);
riscv_csr_predicate_fn predicate;
- int bitsize = 16 << env->misa_mxl_max;
+ int bitsize = 16 << mcc->misa_mxl_max;
int i;
#if !defined(CONFIG_USER_ONLY)
@@ -310,6 +313,7 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
if (env->misa_ext & RVD) {
@@ -326,7 +330,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
ricsv_gen_dynamic_vector_xml(cs, base_reg),
"riscv-vector.xml", 0);
}
- switch (env->misa_mxl_max) {
+ switch (mcc->misa_mxl_max) {
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 680a729cd89a..35a5e6f5f9d0 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -1619,14 +1619,14 @@ static void kvm_cpu_accel_register_types(void)
}
type_init(kvm_cpu_accel_register_types);
-static void riscv_host_cpu_init(Object *obj)
+static void riscv_host_cpu_class_init(ObjectClass *c, void *data)
{
- CPURISCVState *env = &RISCV_CPU(obj)->env;
+ RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
#if defined(TARGET_RISCV32)
- env->misa_mxl_max = env->misa_mxl = MXL_RV32;
+ mcc->misa_mxl_max = MXL_RV32;
#elif defined(TARGET_RISCV64)
- env->misa_mxl_max = env->misa_mxl = MXL_RV64;
+ mcc->misa_mxl_max = MXL_RV64;
#endif
}
@@ -1634,7 +1634,7 @@ static const TypeInfo riscv_kvm_cpu_type_infos[] = {
{
.name = TYPE_RISCV_CPU_HOST,
.parent = TYPE_RISCV_CPU,
- .instance_init = riscv_host_cpu_init,
+ .class_init = riscv_host_cpu_class_init,
}
};
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 72fe2374dc2a..81cf22894e0e 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -178,10 +178,9 @@ static const VMStateDescription vmstate_pointermasking = {
static bool rv128_needed(void *opaque)
{
- RISCVCPU *cpu = opaque;
- CPURISCVState *env = &cpu->env;
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(opaque);
- return env->misa_mxl_max == MXL_RV128;
+ return mcc->misa_mxl_max == MXL_RV128;
}
static const VMStateDescription vmstate_rv128 = {
@@ -372,7 +371,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.vext_ver, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl, RISCVCPU),
VMSTATE_UINT32(env.misa_ext, RISCVCPU),
- VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
+ VMSTATE_UNUSED(4),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index b85b0d036a61..20062acd0f0b 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -272,10 +272,9 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
{
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPUClass *cc = CPU_CLASS(mcc);
- CPURISCVState *env = &cpu->env;
/* Validate that MISA_MXL is set properly. */
- switch (env->misa_mxl_max) {
+ switch (mcc->misa_mxl_max) {
#ifdef TARGET_RISCV64
case MXL_RV64:
case MXL_RV128:
@@ -443,6 +442,7 @@ static void riscv_cpu_validate_g(RISCVCPU *cpu)
*/
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
{
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
@@ -605,7 +605,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcb), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmp), true);
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcmt), true);
- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
}
}
@@ -613,7 +613,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
/* zca, zcd and zcf has a PRIV 1.12.0 restriction */
if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zca), true);
- if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
+ if (riscv_has_ext(env, RVF) && mcc->misa_mxl_max == MXL_RV32) {
cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zcf), true);
}
if (riscv_has_ext(env, RVD)) {
@@ -621,7 +621,7 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
- if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+ if (mcc->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
error_setg(errp, "Zcf extension is only relevant to RV32");
return;
}
@@ -1334,7 +1334,7 @@ static void riscv_init_max_cpu_extensions(Object *obj)
const RISCVCPUMultiExtConfig *prop;
/* Enable RVG, RVJ and RVV that are disabled by default */
- riscv_cpu_set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV);
+ riscv_cpu_set_misa_ext(env, env->misa_ext | RVG | RVJ | RVV);
for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
isa_ext_update_enabled(cpu, prop->offset, true);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 071fbad7ef43..20dbc737d775 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1168,6 +1168,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
CPURISCVState *env = cpu_env(cs);
+ RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
RISCVCPU *cpu = RISCV_CPU(cs);
uint32_t tb_flags = ctx->base.tb->flags;
@@ -1189,7 +1190,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO);
ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
- ctx->misa_mxl_max = env->misa_mxl_max;
+ ctx->misa_mxl_max = mcc->misa_mxl_max;
ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL);
ctx->cs = cs;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v9 4/4] target/riscv: Validate misa_mxl_max only once
2024-01-15 6:31 [PATCH v9 0/4] gdbstub and TCG plugin improvements Akihiko Odaki
` (2 preceding siblings ...)
2024-01-15 6:31 ` [PATCH v9 3/4] target/riscv: Move misa_mxl_max to class Akihiko Odaki
@ 2024-01-15 6:31 ` Akihiko Odaki
3 siblings, 0 replies; 5+ messages in thread
From: Akihiko Odaki @ 2024-01-15 6:31 UTC (permalink / raw)
To: Palmer Dabbelt, Alistair Francis, Bin Meng, Weiwei Li,
Daniel Henrique Barboza, Liu Zhiwei, Alex Bennée,
Mikhail Tyutin, Aleksandr Anenkov, Philippe Mathieu-Daudé,
Fabiano Rosas
Cc: qemu-riscv, qemu-devel, Akihiko Odaki
misa_mxl_max is now a class member and initialized only once for each
class. This also moves the initialization of gdb_core_xml_file which
will be referenced before realization in the future.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 21 +++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c | 23 -----------------------
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4b742901e76e..4425bee1275e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1292,6 +1292,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {
MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
};
+static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
+{
+ CPUClass *cc = CPU_CLASS(mcc);
+
+ /* Validate that MISA_MXL is set properly. */
+ switch (mcc->misa_mxl_max) {
+#ifdef TARGET_RISCV64
+ case MXL_RV64:
+ case MXL_RV128:
+ cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
+ break;
+#endif
+ case MXL_RV32:
+ cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
static int riscv_validate_misa_info_idx(uint32_t bit)
{
int idx;
@@ -1833,6 +1853,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
+ riscv_cpu_validate_misa_mxl(mcc);
}
static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 20062acd0f0b..df198ee3a312 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -268,27 +268,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
}
}
-static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)
-{
- RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
- CPUClass *cc = CPU_CLASS(mcc);
-
- /* Validate that MISA_MXL is set properly. */
- switch (mcc->misa_mxl_max) {
-#ifdef TARGET_RISCV64
- case MXL_RV64:
- case MXL_RV128:
- cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
- break;
-#endif
- case MXL_RV32:
- cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
- default:
- g_assert_not_reached();
- }
-}
-
static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
@@ -935,8 +914,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)
return false;
}
- riscv_cpu_validate_misa_mxl(cpu);
-
#ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env;
Error *local_err = NULL;
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-01-15 6:33 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-01-15 6:31 [PATCH v9 0/4] gdbstub and TCG plugin improvements Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 1/4] hw/riscv: Use misa_mxl instead of misa_mxl_max Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 2/4] target/riscv: Remove misa_mxl validation Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 3/4] target/riscv: Move misa_mxl_max to class Akihiko Odaki
2024-01-15 6:31 ` [PATCH v9 4/4] target/riscv: Validate misa_mxl_max only once Akihiko Odaki
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