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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	qemu-devel@nongnu.org
Subject: [PATCH 2/8] ppc/spapr|pnv: Remove SAO from pa-features when running MTTCG
Date: Fri, 19 Jan 2024 00:09:36 +1000	[thread overview]
Message-ID: <20240118140942.164319-3-npiggin@gmail.com> (raw)
In-Reply-To: <20240118140942.164319-1-npiggin@gmail.com>

SAO is a page table attribute that strengthens the memory ordering of
accesses. QEMU with MTTCG does not implement this, so clear it in
ibm,pa-features. There is a complication with spapr migration that is
addressed with comments, it is not a new problem here.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 hw/ppc/pnv.c   |  5 +++++
 hw/ppc/spapr.c | 15 +++++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b949398689..4969fbdb05 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -158,6 +158,11 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
     char *nodename;
     int cpus_offset = get_cpus_node(fdt);
 
+    if (qemu_tcg_mttcg_enabled()) {
+        /* SSO (SAO) ordering is not supported under MTTCG. */
+        pa_features[4 + 2] &= ~0x80;
+    }
+
     nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
     offset = fdt_add_subnode(fdt, cpus_offset, nodename);
     _FDT(offset);
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 021b1a00e1..1c79d5670d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -284,6 +284,21 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
         return;
     }
 
+    if (qemu_tcg_mttcg_enabled()) {
+        /*
+         * SSO (SAO) ordering is not supported under MTTCG, so disable it.
+         * There is no cap for this, so there is a migration bug here.
+         * However don't disable it entirely, to allow it to be used under
+         * KVM. This is a minor concern because:
+         * - SAO is an obscure an rarely (if ever) used feature.
+         * - SAO is removed from POWER10 / v3.1, so there is already a
+         *   migration problem today.
+         * - Linux does not test this pa-features bit today anyway, so it's
+         *   academic.
+         */
+        pa_features[4 + 2] &= ~0x80;
+    }
+
     if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
         /*
          * Note: we keep CI large pages off by default because a 64K capable
-- 
2.42.0



  parent reply	other threads:[~2024-01-18 14:12 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-18 14:09 [PATCH 0/8] ppc: Update targets for Power machines (spapr and pnv) Nicholas Piggin
2024-01-18 14:09 ` [PATCH 1/8] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-01-18 14:09 ` Nicholas Piggin [this message]
2024-01-19  0:23   ` [PATCH 2/8] ppc/spapr|pnv: Remove SAO from pa-features when running MTTCG David Gibson
2024-01-23  1:57     ` Nicholas Piggin
2024-01-25  3:11       ` David Gibson
2024-01-25  7:08         ` Nicholas Piggin
2024-01-18 14:09 ` [PATCH 3/8] ppc/spapr: Remove copy-paste from pa-features under TCG Nicholas Piggin
2024-01-18 14:09 ` [PATCH 4/8] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-01-18 14:09 ` [PATCH 5/8] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-01-18 14:09 ` [PATCH 6/8] ppc/pnv: Permit ibm,pa-features set per machine variant Nicholas Piggin
2024-01-18 14:09 ` [PATCH 7/8] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-01-18 14:09 ` [PATCH 8/8] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-01-19  8:59   ` Cédric Le Goater

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