From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Frédéric Barrat" <fbarrat@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"David Gibson" <david@gibson.dropbear.id.au>,
"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
qemu-devel@nongnu.org
Subject: [PATCH 6/8] ppc/pnv: Permit ibm,pa-features set per machine variant
Date: Fri, 19 Jan 2024 00:09:40 +1000 [thread overview]
Message-ID: <20240118140942.164319-7-npiggin@gmail.com> (raw)
In-Reply-To: <20240118140942.164319-1-npiggin@gmail.com>
This allows different pa-features for powernv8/9/10.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
hw/ppc/pnv.c | 41 +++++++++++++++++++++++++++++------------
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4969fbdb05..0a144402d7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -133,7 +133,7 @@ static int get_cpus_node(void *fdt)
* device tree, used in XSCOM to address cores and in interrupt
* servers.
*/
-static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
+static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
{
PowerPCCPU *cpu = pc->threads[0];
CPUState *cs = CPU(cpu);
@@ -149,11 +149,6 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
uint32_t cpufreq = 1000000000;
uint32_t page_sizes_prop[64];
size_t page_sizes_prop_size;
- const uint8_t pa_features[] = { 24, 0,
- 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
- 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
- 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
int offset;
char *nodename;
int cpus_offset = get_cpus_node(fdt);
@@ -241,15 +236,14 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
page_sizes_prop, page_sizes_prop_size)));
}
- _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
- pa_features, sizeof(pa_features))));
-
/* Build interrupt servers properties */
for (i = 0; i < smt_threads; i++) {
servers_prop[i] = cpu_to_be32(pc->pir + i);
}
_FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
servers_prop, sizeof(*servers_prop) * smt_threads)));
+
+ return offset;
}
static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
@@ -304,6 +298,17 @@ PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb)
return chip;
}
+/*
+ * Same as spapr pa_features_207 except pnv always enables CI largepages bit.
+ * HTM is always enabled because TCG does implement HTM, it's just a
+ * degenerate implementation.
+ */
+static const uint8_t pa_features_207[] = { 24, 0,
+ 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
+
static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
{
static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
@@ -316,8 +321,12 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
/* Interrupt Control Presenters (ICP). One per core. */
pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
@@ -340,8 +349,12 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
- pnv_dt_core(chip, pnv_core, fdt);
+ offset = pnv_dt_core(chip, pnv_core, fdt);
+
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
@@ -363,8 +376,12 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pnv_core = chip->cores[i];
+ int offset;
+
+ offset = pnv_dt_core(chip, pnv_core, fdt);
- pnv_dt_core(chip, pnv_core, fdt);
+ _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
+ pa_features_207, sizeof(pa_features_207))));
}
if (chip->ram_size) {
--
2.42.0
next prev parent reply other threads:[~2024-01-18 14:13 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 14:09 [PATCH 0/8] ppc: Update targets for Power machines (spapr and pnv) Nicholas Piggin
2024-01-18 14:09 ` [PATCH 1/8] target/ppc: POWER10 does not have transactional memory Nicholas Piggin
2024-01-18 14:09 ` [PATCH 2/8] ppc/spapr|pnv: Remove SAO from pa-features when running MTTCG Nicholas Piggin
2024-01-19 0:23 ` David Gibson
2024-01-23 1:57 ` Nicholas Piggin
2024-01-25 3:11 ` David Gibson
2024-01-25 7:08 ` Nicholas Piggin
2024-01-18 14:09 ` [PATCH 3/8] ppc/spapr: Remove copy-paste from pa-features under TCG Nicholas Piggin
2024-01-18 14:09 ` [PATCH 4/8] ppc/spapr: Adjust ibm,pa-features for POWER9 Nicholas Piggin
2024-01-18 14:09 ` [PATCH 5/8] ppc/spapr: Add pa-features for POWER10 machines Nicholas Piggin
2024-01-18 14:09 ` Nicholas Piggin [this message]
2024-01-18 14:09 ` [PATCH 7/8] ppc/pnv: Set POWER9, POWER10 ibm,pa-features bits Nicholas Piggin
2024-01-18 14:09 ` [PATCH 8/8] ppc/pnv: Update skiboot to v7.1 Nicholas Piggin
2024-01-19 8:59 ` Cédric Le Goater
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