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From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Nicholas Piggin" <npiggin@gmail.com>,
	"Cédric Le Goater" <clg@kaod.org>,
	"Frédéric Barrat" <fbarrat@linux.ibm.com>,
	"Daniel Henrique Barboza" <danielhb413@gmail.com>,
	"David Gibson" <david@gibson.dropbear.id.au>,
	"Harsh Prateek Bora" <harshpb@linux.ibm.com>,
	qemu-devel@nongnu.org
Subject: [PATCH 10/26] ppc/pnv: Wire ChipTOD model to powernv9 and powernv10 machines
Date: Fri, 19 Jan 2024 01:06:28 +1000	[thread overview]
Message-ID: <20240118150644.177371-11-npiggin@gmail.com> (raw)
In-Reply-To: <20240118150644.177371-1-npiggin@gmail.com>

Wire the ChipTOD model to powernv9 and powernv10 machines.

Suggested-by-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 include/hw/ppc/pnv_chip.h |  3 +++
 hw/ppc/pnv.c              | 30 ++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/include/hw/ppc/pnv_chip.h b/include/hw/ppc/pnv_chip.h
index 0ab5c42308..bfc4772cf3 100644
--- a/include/hw/ppc/pnv_chip.h
+++ b/include/hw/ppc/pnv_chip.h
@@ -2,6 +2,7 @@
 #define PPC_PNV_CHIP_H
 
 #include "hw/pci-host/pnv_phb4.h"
+#include "hw/ppc/pnv_chiptod.h"
 #include "hw/ppc/pnv_core.h"
 #include "hw/ppc/pnv_homer.h"
 #include "hw/ppc/pnv_lpc.h"
@@ -78,6 +79,7 @@ struct Pnv9Chip {
     PnvXive      xive;
     Pnv9Psi      psi;
     PnvLpcController lpc;
+    PnvChipTOD   chiptod;
     PnvOCC       occ;
     PnvSBE       sbe;
     PnvHomer     homer;
@@ -110,6 +112,7 @@ struct Pnv10Chip {
     PnvXive2     xive;
     Pnv9Psi      psi;
     PnvLpcController lpc;
+    PnvChipTOD   chiptod;
     PnvOCC       occ;
     PnvSBE       sbe;
     PnvHomer     homer;
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 9db8fcd19e..f0456e2acf 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1505,6 +1505,8 @@ static void pnv_chip_power9_instance_init(Object *obj)
 
     object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
 
+    object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD);
+
     object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
 
     object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
@@ -1651,6 +1653,19 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
                                             (uint64_t) PNV9_LPCM_BASE(chip));
 
+    /* ChipTOD */
+    object_property_set_bool(OBJECT(&chip9->chiptod), "primary",
+                             chip->chip_id == 0, &error_abort);
+    object_property_set_bool(OBJECT(&chip9->chiptod), "secondary",
+                             chip->chip_id == 1, &error_abort);
+    object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip),
+                             &error_abort);
+    if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) {
+        return;
+    }
+    pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE,
+                            &chip9->chiptod.xscom_regs);
+
     /* Create the simplified OCC model */
     if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
         return;
@@ -1763,6 +1778,8 @@ static void pnv_chip_power10_instance_init(Object *obj)
                               "xive-fabric");
     object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
     object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
+    object_initialize_child(obj, "chiptod", &chip10->chiptod,
+                            TYPE_PNV10_CHIPTOD);
     object_initialize_child(obj, "occ",  &chip10->occ, TYPE_PNV10_OCC);
     object_initialize_child(obj, "sbe",  &chip10->sbe, TYPE_PNV10_SBE);
     object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
@@ -1896,6 +1913,19 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
     chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
                                             (uint64_t) PNV10_LPCM_BASE(chip));
 
+    /* ChipTOD */
+    object_property_set_bool(OBJECT(&chip10->chiptod), "primary",
+                             chip->chip_id == 0, &error_abort);
+    object_property_set_bool(OBJECT(&chip10->chiptod), "secondary",
+                             chip->chip_id == 1, &error_abort);
+    object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip),
+                             &error_abort);
+    if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) {
+        return;
+    }
+    pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE,
+                            &chip10->chiptod.xscom_regs);
+
     /* Create the simplified OCC model */
     if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
         return;
-- 
2.42.0



  parent reply	other threads:[~2024-01-18 15:07 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-18 15:06 [PATCH 00/26] target/ppc: TCG improvements and fixes Nicholas Piggin
2024-01-18 15:06 ` [PATCH 01/26] target/ppc: Fix crash on machine check caused by ifetch Nicholas Piggin
2024-01-18 15:06 ` [PATCH 02/26] target/ppc: Prevent supervisor from modifying MSR[ME] Nicholas Piggin
2024-01-18 15:06 ` [PATCH 03/26] spapr: set MSR[ME] and MSR[FP] on client entry Nicholas Piggin
2024-01-18 15:06 ` [PATCH 04/26] target/ppc: Rename registers to match ISA Nicholas Piggin
2024-01-18 15:06 ` [PATCH 05/26] target/ppc: Update gdbstub to read SPR's CFAR, DEC, HDEC, TB-L/U Nicholas Piggin
2024-01-18 15:06 ` [PATCH 06/26] target/ppc: Rename TBL to TB on 64-bit Nicholas Piggin
2024-01-18 15:06 ` [PATCH 07/26] target/ppc: Improve timebase register defines naming Nicholas Piggin
2024-01-18 15:06 ` [PATCH 08/26] target/ppc: Fix move-to timebase SPR access permissions Nicholas Piggin
2024-01-18 15:06 ` [PATCH 09/26] pnv/chiptod: Add POWER9/10 chiptod model Nicholas Piggin
2024-01-18 15:06 ` Nicholas Piggin [this message]
2024-01-18 15:06 ` [PATCH 11/26] pnv/chiptod: Implement the ChipTOD to Core transfer Nicholas Piggin
2024-01-18 15:06 ` [PATCH 12/26] target/ppc: Implement core timebase state machine and TFMR Nicholas Piggin
2024-01-18 15:06 ` [PATCH 13/26] target/ppc: Add SMT support to time facilities Nicholas Piggin
2024-01-18 15:06 ` [PATCH 14/26] target/ppc: Add new hflags to support BHRB Nicholas Piggin
2024-01-18 15:06 ` [PATCH 15/26] target/ppc: Add recording of taken branches to BHRB Nicholas Piggin
2024-01-18 15:06 ` [PATCH 16/26] target/ppc: Add clrbhrb and mfbhrbe instructions Nicholas Piggin
2024-01-18 15:06 ` [PATCH 17/26] target/ppc: Add migration support for BHRB Nicholas Piggin
2024-01-18 15:06 ` [PATCH 18/26] target/ppc: BookE DECAR SPR is 32-bit Nicholas Piggin
2024-01-18 15:06 ` [PATCH 19/26] target/ppc: Wire up BookE ATB registers for e500 family Nicholas Piggin
2024-01-18 15:06 ` [PATCH 20/26] target/ppc: Add PPR32 SPR Nicholas Piggin
2024-01-18 15:06 ` [PATCH 21/26] target/ppc: add helper to write per-LPAR SPRs Nicholas Piggin
2024-01-18 15:06 ` [PATCH 22/26] target/ppc: Add SMT support to simple SPRs Nicholas Piggin
2024-01-18 15:06 ` [PATCH 23/26] target/ppc: Add SMT support to PTCR SPR Nicholas Piggin
2024-01-18 15:06 ` [PATCH 24/26] target/ppc: Implement LDBAR, TTR SPRs Nicholas Piggin
2024-01-18 15:06 ` [PATCH 25/26] target/ppc: Implement SPRC/SPRD SPRs Nicholas Piggin
2024-01-18 15:06 ` [PATCH 26/26] target/ppc: add SMT support to msgsnd broadcast Nicholas Piggin
2024-01-19  8:58 ` [PATCH 00/26] target/ppc: TCG improvements and fixes Cédric Le Goater
2024-01-23  1:53   ` Nicholas Piggin

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