From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,
qemu-block@nongnu.org, qemu-arm@nongnu.org,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>
Subject: [PULL 22/36] system/watchpoint: Move TCG specific code to accel/tcg/
Date: Fri, 19 Jan 2024 12:34:51 +0100 [thread overview]
Message-ID: <20240119113507.31951-23-philmd@linaro.org> (raw)
In-Reply-To: <20240119113507.31951-1-philmd@linaro.org>
Keep system/watchpoint.c accelerator-agnostic by moving
TCG specific code to accel/tcg/watchpoint.c. Update meson.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240111162032.43378-1-philmd@linaro.org>
---
accel/tcg/watchpoint.c | 143 +++++++++++++++++++++++++++++++++++++++++
system/watchpoint.c | 124 -----------------------------------
accel/tcg/meson.build | 1 +
3 files changed, 144 insertions(+), 124 deletions(-)
create mode 100644 accel/tcg/watchpoint.c
diff --git a/accel/tcg/watchpoint.c b/accel/tcg/watchpoint.c
new file mode 100644
index 0000000000..d3aab11458
--- /dev/null
+++ b/accel/tcg/watchpoint.c
@@ -0,0 +1,143 @@
+/*
+ * CPU watchpoints
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "qemu/error-report.h"
+#include "exec/exec-all.h"
+#include "exec/translate-all.h"
+#include "sysemu/tcg.h"
+#include "sysemu/replay.h"
+#include "hw/core/tcg-cpu-ops.h"
+#include "hw/core/cpu.h"
+
+/*
+ * Return true if this watchpoint address matches the specified
+ * access (ie the address range covered by the watchpoint overlaps
+ * partially or completely with the address range covered by the
+ * access).
+ */
+static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
+ vaddr addr, vaddr len)
+{
+ /*
+ * We know the lengths are non-zero, but a little caution is
+ * required to avoid errors in the case where the range ends
+ * exactly at the top of the address space and so addr + len
+ * wraps round to zero.
+ */
+ vaddr wpend = wp->vaddr + wp->len - 1;
+ vaddr addrend = addr + len - 1;
+
+ return !(addr > wpend || wp->vaddr > addrend);
+}
+
+/* Return flags for watchpoints that match addr + prot. */
+int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
+{
+ CPUWatchpoint *wp;
+ int ret = 0;
+
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
+ if (watchpoint_address_matches(wp, addr, len)) {
+ ret |= wp->flags;
+ }
+ }
+ return ret;
+}
+
+/* Generate a debug exception if a watchpoint has been hit. */
+void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
+ MemTxAttrs attrs, int flags, uintptr_t ra)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ CPUWatchpoint *wp;
+
+ assert(tcg_enabled());
+ if (cpu->watchpoint_hit) {
+ /*
+ * We re-entered the check after replacing the TB.
+ * Now raise the debug interrupt so that it will
+ * trigger after the current instruction.
+ */
+ bql_lock();
+ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
+ bql_unlock();
+ return;
+ }
+
+ if (cc->tcg_ops->adjust_watchpoint_address) {
+ /* this is currently used only by ARM BE32 */
+ addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
+ }
+
+ assert((flags & ~BP_MEM_ACCESS) == 0);
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
+ int hit_flags = wp->flags & flags;
+
+ if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
+ if (replay_running_debug()) {
+ /*
+ * replay_breakpoint reads icount.
+ * Force recompile to succeed, because icount may
+ * be read only at the end of the block.
+ */
+ if (!cpu->neg.can_do_io) {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
+ cpu_loop_exit_restore(cpu, ra);
+ }
+ /*
+ * Don't process the watchpoints when we are
+ * in a reverse debugging operation.
+ */
+ replay_breakpoint();
+ return;
+ }
+
+ wp->flags |= hit_flags << BP_HIT_SHIFT;
+ wp->hitaddr = MAX(addr, wp->vaddr);
+ wp->hitattrs = attrs;
+
+ if (wp->flags & BP_CPU
+ && cc->tcg_ops->debug_check_watchpoint
+ && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ continue;
+ }
+ cpu->watchpoint_hit = wp;
+
+ mmap_lock();
+ /* This call also restores vCPU state */
+ tb_check_watchpoint(cpu, ra);
+ if (wp->flags & BP_STOP_BEFORE_ACCESS) {
+ cpu->exception_index = EXCP_DEBUG;
+ mmap_unlock();
+ cpu_loop_exit(cpu);
+ } else {
+ /* Force execution of one insn next time. */
+ cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
+ mmap_unlock();
+ cpu_loop_exit_noexc(cpu);
+ }
+ } else {
+ wp->flags &= ~BP_WATCHPOINT_HIT;
+ }
+ }
+}
diff --git a/system/watchpoint.c b/system/watchpoint.c
index b76007ebf6..2aa2a9ea63 100644
--- a/system/watchpoint.c
+++ b/system/watchpoint.c
@@ -18,13 +18,8 @@
*/
#include "qemu/osdep.h"
-#include "qemu/main-loop.h"
#include "qemu/error-report.h"
#include "exec/exec-all.h"
-#include "exec/translate-all.h"
-#include "sysemu/tcg.h"
-#include "sysemu/replay.h"
-#include "hw/core/tcg-cpu-ops.h"
#include "hw/core/cpu.h"
/* Add a watchpoint. */
@@ -103,122 +98,3 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
}
}
}
-
-#ifdef CONFIG_TCG
-
-/*
- * Return true if this watchpoint address matches the specified
- * access (ie the address range covered by the watchpoint overlaps
- * partially or completely with the address range covered by the
- * access).
- */
-static inline bool watchpoint_address_matches(CPUWatchpoint *wp,
- vaddr addr, vaddr len)
-{
- /*
- * We know the lengths are non-zero, but a little caution is
- * required to avoid errors in the case where the range ends
- * exactly at the top of the address space and so addr + len
- * wraps round to zero.
- */
- vaddr wpend = wp->vaddr + wp->len - 1;
- vaddr addrend = addr + len - 1;
-
- return !(addr > wpend || wp->vaddr > addrend);
-}
-
-/* Return flags for watchpoints that match addr + prot. */
-int cpu_watchpoint_address_matches(CPUState *cpu, vaddr addr, vaddr len)
-{
- CPUWatchpoint *wp;
- int ret = 0;
-
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- if (watchpoint_address_matches(wp, addr, len)) {
- ret |= wp->flags;
- }
- }
- return ret;
-}
-
-/* Generate a debug exception if a watchpoint has been hit. */
-void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len,
- MemTxAttrs attrs, int flags, uintptr_t ra)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- CPUWatchpoint *wp;
-
- assert(tcg_enabled());
- if (cpu->watchpoint_hit) {
- /*
- * We re-entered the check after replacing the TB.
- * Now raise the debug interrupt so that it will
- * trigger after the current instruction.
- */
- bql_lock();
- cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
- bql_unlock();
- return;
- }
-
- if (cc->tcg_ops->adjust_watchpoint_address) {
- /* this is currently used only by ARM BE32 */
- addr = cc->tcg_ops->adjust_watchpoint_address(cpu, addr, len);
- }
-
- assert((flags & ~BP_MEM_ACCESS) == 0);
- QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- int hit_flags = wp->flags & flags;
-
- if (hit_flags && watchpoint_address_matches(wp, addr, len)) {
- if (replay_running_debug()) {
- /*
- * replay_breakpoint reads icount.
- * Force recompile to succeed, because icount may
- * be read only at the end of the block.
- */
- if (!cpu->neg.can_do_io) {
- /* Force execution of one insn next time. */
- cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
- cpu_loop_exit_restore(cpu, ra);
- }
- /*
- * Don't process the watchpoints when we are
- * in a reverse debugging operation.
- */
- replay_breakpoint();
- return;
- }
-
- wp->flags |= hit_flags << BP_HIT_SHIFT;
- wp->hitaddr = MAX(addr, wp->vaddr);
- wp->hitattrs = attrs;
-
- if (wp->flags & BP_CPU
- && cc->tcg_ops->debug_check_watchpoint
- && !cc->tcg_ops->debug_check_watchpoint(cpu, wp)) {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- continue;
- }
- cpu->watchpoint_hit = wp;
-
- mmap_lock();
- /* This call also restores vCPU state */
- tb_check_watchpoint(cpu, ra);
- if (wp->flags & BP_STOP_BEFORE_ACCESS) {
- cpu->exception_index = EXCP_DEBUG;
- mmap_unlock();
- cpu_loop_exit(cpu);
- } else {
- /* Force execution of one insn next time. */
- cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(cpu);
- mmap_unlock();
- cpu_loop_exit_noexc(cpu);
- }
- } else {
- wp->flags &= ~BP_WATCHPOINT_HIT;
- }
- }
-}
-
-#endif /* CONFIG_TCG */
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index d25638d6c1..c15ac9ac8f 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -24,6 +24,7 @@ specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
'cputlb.c',
+ 'watchpoint.c',
))
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
--
2.41.0
next prev parent reply other threads:[~2024-01-19 11:43 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-19 11:34 [PULL 00/36] HW core patches for 2024-01-19 Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 01/36] hw/timer/hpet: Convert DPRINTF to trace events Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 02/36] backends/cryptodev: Do not ignore throttle/backends Errors Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 04/36] accel: Do not set CPUState::can_do_io " Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 05/36] target/xtensa: use generic instruction breakpoint infrastructure Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 06/36] tests/tcg/xtensa: add icount/ibreak priority test Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 07/36] accel/tcg: Remove unused tb_invalidate_phys_addr() Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 08/36] accel/tcg: Remove tb_invalidate_phys_page() from system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 09/36] target/alpha: Extract clk_helper.c from sys_helper.c Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 10/36] target/alpha: Only build sys_helper.c on system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 11/36] system/cpu-timers: Have icount_configure() return a boolean Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 12/36] system/cpu-timers: Introduce ICountMode enumerator Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 14/36] util/async: Only call icount_notify_exit() if icount is enabled Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 15/36] target/sh4: Deprecate the shix machine Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 16/36] hw/block: Deprecate the TC58128 block device Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 17/36] hw/i386/pc_piix: Make piix_intx_routing_notifier_xen() more device independent Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 18/36] hw/pflash: refactor pflash_data_write() Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 19/36] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 20/36] hw/pflash: implement update buffer for block writes Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 21/36] system/replay: Restrict icount to system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` Philippe Mathieu-Daudé [this message]
2024-01-19 11:34 ` [PULL 23/36] cpus: Restrict 'start-powered-off' property " Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 24/36] accel: Rename accel_init_ops_interfaces() to include 'system' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 25/36] hw/core/cpu: Rename cpu_class_init() to include 'common' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 26/36] hw/s390x: Rename cpu_class_init() to include 'sclp' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 27/36] target/i386: Rename tcg_cpu_FOO() to include 'x86' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 29/36] hw/scsi/esp-pci: use correct address register for PCI DMA transfers Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 32/36] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 33/36] hw/elf_ops: Ignore loadable segments with zero size Philippe Mathieu-Daudé
2024-01-24 20:48 ` Alex Bennée
2024-01-19 11:35 ` [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 35/36] MAINTAINERS: Update hw/core/cpu.c entry Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 36/36] configure: Add linux header compile support for LoongArch Philippe Mathieu-Daudé
2024-01-19 16:41 ` [PULL 00/36] HW core patches for 2024-01-19 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240119113507.31951-23-philmd@linaro.org \
--to=philmd@linaro.org \
--cc=pbonzini@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-block@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).