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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, qemu-s390x@nongnu.org,
	qemu-block@nongnu.org, qemu-arm@nongnu.org,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	"Guenter Roeck" <linux@roeck-us.net>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Fam Zheng" <fam@euphon.net>
Subject: [PULL 31/36] hw/scsi/esp-pci: synchronise setting of DMA_STAT_DONE with ESP completion interrupt
Date: Fri, 19 Jan 2024 12:35:00 +0100	[thread overview]
Message-ID: <20240119113507.31951-32-philmd@linaro.org> (raw)
In-Reply-To: <20240119113507.31951-1-philmd@linaro.org>

From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>

The setting of DMA_STAT_DONE at the end of a DMA transfer can be configured to
generate an interrupt, however the Linux driver manually checks for DMA_STAT_DONE
being set and if it is, considers that a DMA transfer has completed.

If DMA_STAT_DONE is set but the ESP device isn't indicating an interrupt then
the Linux driver considers this to be a spurious interrupt. However this can
occur in QEMU as there is a delay between the end of DMA transfer where
DMA_STAT_DONE is set, and the ESP device raising its completion interrupt.

This appears to be an incorrect assumption in the Linux driver as the ESP and
PCI DMA interrupt sources are separate (and may not be raised exactly
together), however we can work around this by synchronising the setting of
DMA_STAT_DONE at the end of a DMA transfer with the ESP completion interrupt.

In conjunction with the previous commit Linux is now able to correctly boot
from an am53c974 PCI SCSI device on the hppa C3700 machine without emitting
"iget: checksum invalid" and "Spurious irq, sreg=10" errors.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Message-ID: <20240112131529.515642-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/scsi/esp-pci.c | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
index 15dc3c004d..875a49199d 100644
--- a/hw/scsi/esp-pci.c
+++ b/hw/scsi/esp-pci.c
@@ -93,6 +93,18 @@ static void esp_irq_handler(void *opaque, int irq_num, int level)
 
     if (level) {
         pci->dma_regs[DMA_STAT] |= DMA_STAT_SCSIINT;
+
+        /*
+         * If raising the ESP IRQ to indicate end of DMA transfer, set
+         * DMA_STAT_DONE at the same time. In theory this should be done in
+         * esp_pci_dma_memory_rw(), however there is a delay between setting
+         * DMA_STAT_DONE and the ESP IRQ arriving which is visible to the
+         * guest that can cause confusion e.g. Linux
+         */
+        if ((pci->dma_regs[DMA_CMD] & DMA_CMD_MASK) == 0x3 &&
+            pci->dma_regs[DMA_WBC] == 0) {
+                pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
+        }
     } else {
         pci->dma_regs[DMA_STAT] &= ~DMA_STAT_SCSIINT;
     }
@@ -306,9 +318,6 @@ static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
     /* update status registers */
     pci->dma_regs[DMA_WBC] -= len;
     pci->dma_regs[DMA_WAC] += len;
-    if (pci->dma_regs[DMA_WBC] == 0) {
-        pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
-    }
 }
 
 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
@@ -363,24 +372,13 @@ static const VMStateDescription vmstate_esp_pci_scsi = {
     }
 };
 
-static void esp_pci_command_complete(SCSIRequest *req, size_t resid)
-{
-    ESPState *s = req->hba_private;
-    PCIESPState *pci = container_of(s, PCIESPState, esp);
-
-    esp_command_complete(req, resid);
-    pci->dma_regs[DMA_WBC] = 0;
-    pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
-    esp_pci_update_irq(pci);
-}
-
 static const struct SCSIBusInfo esp_pci_scsi_info = {
     .tcq = false,
     .max_target = ESP_MAX_DEVS,
     .max_lun = 7,
 
     .transfer_data = esp_transfer_data,
-    .complete = esp_pci_command_complete,
+    .complete = esp_command_complete,
     .cancel = esp_request_cancelled,
 };
 
-- 
2.41.0



  parent reply	other threads:[~2024-01-19 11:43 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-01-19 11:34 [PULL 00/36] HW core patches for 2024-01-19 Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 01/36] hw/timer/hpet: Convert DPRINTF to trace events Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 02/36] backends/cryptodev: Do not ignore throttle/backends Errors Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 03/36] accel: Do not set CPUState::tcg_cflags in non-TCG accels Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 04/36] accel: Do not set CPUState::can_do_io " Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 05/36] target/xtensa: use generic instruction breakpoint infrastructure Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 06/36] tests/tcg/xtensa: add icount/ibreak priority test Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 07/36] accel/tcg: Remove unused tb_invalidate_phys_addr() Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 08/36] accel/tcg: Remove tb_invalidate_phys_page() from system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 09/36] target/alpha: Extract clk_helper.c from sys_helper.c Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 10/36] target/alpha: Only build sys_helper.c on system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 11/36] system/cpu-timers: Have icount_configure() return a boolean Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 12/36] system/cpu-timers: Introduce ICountMode enumerator Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 13/36] target/arm: Ensure icount is enabled when emulating INST_RETIRED Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 14/36] util/async: Only call icount_notify_exit() if icount is enabled Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 15/36] target/sh4: Deprecate the shix machine Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 16/36] hw/block: Deprecate the TC58128 block device Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 17/36] hw/i386/pc_piix: Make piix_intx_routing_notifier_xen() more device independent Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 18/36] hw/pflash: refactor pflash_data_write() Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 19/36] hw/pflash: use ldn_{be,le}_p and stn_{be,le}_p Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 20/36] hw/pflash: implement update buffer for block writes Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 21/36] system/replay: Restrict icount to system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 22/36] system/watchpoint: Move TCG specific code to accel/tcg/ Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 23/36] cpus: Restrict 'start-powered-off' property to system emulation Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 24/36] accel: Rename accel_init_ops_interfaces() to include 'system' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 25/36] hw/core/cpu: Rename cpu_class_init() to include 'common' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 26/36] hw/s390x: Rename cpu_class_init() to include 'sclp' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 27/36] target/i386: Rename tcg_cpu_FOO() to include 'x86' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 28/36] target/riscv: Rename tcg_cpu_FOO() to include 'riscv' Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 29/36] hw/scsi/esp-pci: use correct address register for PCI DMA transfers Philippe Mathieu-Daudé
2024-01-19 11:34 ` [PULL 30/36] hw/scsi/esp-pci: generate PCI interrupt from separate ESP and PCI sources Philippe Mathieu-Daudé
2024-01-19 11:35 ` Philippe Mathieu-Daudé [this message]
2024-01-19 11:35 ` [PULL 32/36] hw/scsi/esp-pci: set DMA_STAT_BCMBLT when BLAST command issued Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 33/36] hw/elf_ops: Ignore loadable segments with zero size Philippe Mathieu-Daudé
2024-01-24 20:48   ` Alex Bennée
2024-01-19 11:35 ` [PULL 34/36] MAINTAINERS: Update Raphael Norwitz email Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 35/36] MAINTAINERS: Update hw/core/cpu.c entry Philippe Mathieu-Daudé
2024-01-19 11:35 ` [PULL 36/36] configure: Add linux header compile support for LoongArch Philippe Mathieu-Daudé
2024-01-19 16:41 ` [PULL 00/36] HW core patches for 2024-01-19 Peter Maydell

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