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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id g4-20020a05600c310400b0040e88d1422esm18936838wmo.31.2024.01.22.04.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 04:59:23 -0800 (PST) Date: Mon, 22 Jan 2024 13:59:22 +0100 From: Andrew Jones To: Heinrich Schuchardt Cc: Palmer Dabbelt , Alistair Francis , Paolo Bonzini , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: Re: [PATCH v2 3/4] target/riscv: SMBIOS support for RISC-V virt machine Message-ID: <20240122-195c4a8d0ece609441068e16@orel> References: <20231229120724.41383-1-heinrich.schuchardt@canonical.com> <20231229120724.41383-4-heinrich.schuchardt@canonical.com> <20240122-4f4cbce3692cd684e0409f9e@orel> <22105210-d8d1-4808-b9ed-41eee71c53ca@canonical.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <22105210-d8d1-4808-b9ed-41eee71c53ca@canonical.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jan 22, 2024 at 01:28:18PM +0100, Heinrich Schuchardt wrote: > On 22.01.24 10:57, Andrew Jones wrote: > > On Fri, Dec 29, 2023 at 01:07:23PM +0100, Heinrich Schuchardt wrote: ... > > > +#if defined(TARGET_RISCV32) > > > + smbios_set_default_processor_family(0x200); > > > +#elif defined(TARGET_RISCV64) > > > + smbios_set_default_processor_family(0x201); > > > +#endif > > > > I think we should use misa_mxl_max to determine the family, rather than > > TARGET_*, because, iirc, we're slowly working our ways towards allowing > > rv32 cpus to be instantiated with qemu-system-riscv64. > > Hello Andrew, > > thank you for reviewing. I guess you mean something like: > > if (riscv_is_32bit(&s->soc[0])) { > smbios_set_default_processor_family(0x200); > #if defined(TARGET_RISCV64) > } else { > smbios_set_default_processor_family(0x201); > #endif > } Yes, but I'm not sure we need the #ifdef around the 64-bit part. > > riscv_is_32bit returns harts->harts[0].env.misa_mxl_max == MXL_RV32. > > Some real hardware has a 32bit hart and multiple 64bit harts. Will QEMU > support mixing harts with different bitness on the virt machine in future? > In that case we would have to revisit the code using misa_mxl_max in > multiple places. > Never say never, but I don't think there has been much effort to support these types of configurations with a single QEMU binary. My googling is failing me right now, but I seem to recall that there may have been efforts to implement Arm big.LITTLE with multiprocess QEMU [1]. IOW, I think we're safe to use misa_mxl_max, since we'll have one for each QEMU instance and we'll use a different QEMU instance for each hart bitness. [1] docs/system/multi-process.rst Thanks, drew