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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id ec32-20020a0564020d6000b0055c4c97b1f2sm1716628edb.91.2024.01.23.00.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:20:20 -0800 (PST) Date: Tue, 23 Jan 2024 09:20:18 +0100 From: Andrew Jones To: Alex =?utf-8?Q?Benn=C3=A9e?= Cc: qemu-devel@nongnu.org, Marcel Apfelbaum , "Edgar E. Iglesias" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Michael Rolnik , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Laurent Vivier , kvm@vger.kernel.org, Yoshinori Sato , Pierrick Bouvier , Palmer Dabbelt , Liu Zhiwei , Laurent Vivier , Yanan Wang , qemu-ppc@nongnu.org, Weiwei Li , qemu-s390x@nongnu.org, =?utf-8?Q?C=C3=A9dric?= Le Goater , Peter Maydell , Alexandre Iooss , John Snow , Mahmoud Mandour , Wainer dos Santos Moschetta , Richard Henderson , Ilya Leoshkevich , Alistair Francis , David Woodhouse , Cleber Rosa , Beraldo Leal , Bin Meng , Nicholas Piggin , Aurelien Jarno , Daniel Henrique Barboza , Daniel Henrique Barboza , Thomas Huth , David Hildenbrand , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , Song Gao , Eduardo Habkost , Brian Cain , Paul Durrant , Akihiko Odaki Subject: Re: [PATCH v3 01/21] hw/riscv: Use misa_mxl instead of misa_mxl_max Message-ID: <20240123-b8d1c55688885bfc9125c42b@orel> References: <20240122145610.413836-1-alex.bennee@linaro.org> <20240122145610.413836-2-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20240122145610.413836-2-alex.bennee@linaro.org> Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, Jan 22, 2024 at 02:55:50PM +0000, Alex Bennée wrote: > From: Akihiko Odaki > > The effective MXL value matters when booting. I'd prefer this commit message get some elaboration. riscv_is_32bit() is used in a variety of contexts, some where it should be reporting the max misa.mxl. However, when used for booting an S-mode kernel it should indeed report the effective mxl. I think we're fine with the change, though, because at init and on reset the effective mxl is set to the max mxl, so, in those contexts, where riscv_is_32bit() should be reporting the max, it does. > > Signed-off-by: Akihiko Odaki > Message-Id: <20240103173349.398526-23-alex.bennee@linaro.org> > Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com> > Signed-off-by: Alex Bennée > --- > hw/riscv/boot.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 0ffca05189f..bc67c0bd189 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -36,7 +36,7 @@ > > bool riscv_is_32bit(RISCVHartArrayState *harts) > { > - return harts->harts[0].env.misa_mxl_max == MXL_RV32; > + return harts->harts[0].env.misa_mxl == MXL_RV32; > } Assuming everyone agrees with what I've written above, then maybe we should write something similar in a comment above this function. Thanks, drew