* [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init()
@ 2024-01-23 6:38 Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 1/8] hw/arm/exynos: " Philippe Mathieu-Daudé
` (7 more replies)
0 siblings, 8 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Following Gavin recent CPU type enforcement cleanups,
restrict more single-CPU ARM machines (here Cortex-A SoC).
Based-on: <20240118200643.29037-1-philmd@linaro.org> (arm-next)
Philippe Mathieu-Daudé (8):
hw/arm/exynos: Check for CPU types in machine_run_board_init()
hw/arm/highbank: Check for CPU types in machine_run_board_init()
hw/arm/vexpress: Check for CPU types in machine_run_board_init()
hw/arm/aspeed/2400: Check for CPU types in machine_run_board_init()
hw/arm/aspeed/2500: Check for CPU types in machine_run_board_init()
hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()
hw/arm/aspeed/1030: Check for CPU types in machine_run_board_init()
hw/arm/zynq: Check for CPU types in machine_run_board_init()
hw/arm/aspeed.c | 40 ++++++++++++++++++++++++++++++++++++++++
hw/arm/exynos4_boards.c | 8 ++++++++
hw/arm/highbank.c | 10 ++++++++++
hw/arm/vexpress.c | 10 ++++++++++
hw/arm/xilinx_zynq.c | 5 +++++
5 files changed, 73 insertions(+)
--
2.41.0
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/8] hw/arm/exynos: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 2/8] hw/arm/highbank: " Philippe Mathieu-Daudé
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/exynos4_boards.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index b0e13eb4f0..01c7618a67 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -34,6 +34,7 @@
#include "hw/qdev-properties.h"
#include "hw/boards.h"
#include "hw/irq.h"
+#include "target/arm/cpu-qom.h"
#define SMDK_LAN9118_BASE_ADDR 0x05000000
@@ -150,12 +151,18 @@ static void smdkc210_init(MachineState *machine)
arm_load_kernel(s->soc.cpu[0], machine, &exynos4_board_binfo);
}
+static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+};
+
static void nuri_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Samsung NURI board (Exynos4210)";
mc->init = nuri_init;
+ mc->valid_cpu_types = valid_cpu_types;
mc->max_cpus = EXYNOS4210_NCPUS;
mc->min_cpus = EXYNOS4210_NCPUS;
mc->default_cpus = EXYNOS4210_NCPUS;
@@ -174,6 +181,7 @@ static void smdkc210_class_init(ObjectClass *oc, void *data)
mc->desc = "Samsung SMDKC210 board (Exynos4210)";
mc->init = smdkc210_init;
+ mc->valid_cpu_types = valid_cpu_types;
mc->max_cpus = EXYNOS4210_NCPUS;
mc->min_cpus = EXYNOS4210_NCPUS;
mc->default_cpus = EXYNOS4210_NCPUS;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/8] hw/arm/highbank: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 1/8] hw/arm/exynos: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 3/8] hw/arm/vexpress: " Philippe Mathieu-Daudé
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/highbank.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index e6e27d69af..67677eb651 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -344,10 +344,15 @@ static void midway_init(MachineState *machine)
static void highbank_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Calxeda Highbank (ECX-1000)";
mc->init = highbank_init;
+ mc->valid_cpu_types = valid_cpu_types;
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
mc->max_cpus = 4;
@@ -363,10 +368,15 @@ static const TypeInfo highbank_type = {
static void midway_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a15"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Calxeda Midway (ECX-2000)";
mc->init = midway_init;
+ mc->valid_cpu_types = valid_cpu_types;
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
mc->max_cpus = 4;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 3/8] hw/arm/vexpress: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 1/8] hw/arm/exynos: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 2/8] hw/arm/highbank: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 4/8] hw/arm/aspeed/2400: " Philippe Mathieu-Daudé
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU types.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/vexpress.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index f1b45245d5..a3561a1b56 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -783,22 +783,32 @@ static void vexpress_class_init(ObjectClass *oc, void *data)
static void vexpress_a9_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
mc->desc = "ARM Versatile Express for Cortex-A9";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
+ mc->valid_cpu_types = valid_cpu_types;
vmc->daughterboard = &a9_daughterboard;
}
static void vexpress_a15_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a15"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
VexpressMachineClass *vmc = VEXPRESS_MACHINE_CLASS(oc);
mc->desc = "ARM Versatile Express for Cortex-A15";
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
+ mc->valid_cpu_types = valid_cpu_types;
vmc->daughterboard = &a15_daughterboard;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/8] hw/arm/aspeed/2400: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2024-01-23 6:38 ` [PATCH 3/8] hw/arm/vexpress: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 9:03 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 5/8] hw/arm/aspeed/2500: " Philippe Mathieu-Daudé
` (3 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index cc59176563..e0e0877b1d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1147,6 +1147,11 @@ static int aspeed_soc_num_cpus(const char *soc_name)
return sc->num_cpus;
}
+static const char * const ast2400_a1_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("arm926"),
+ NULL
+};
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1175,6 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635f";
amc->num_cs = 1;
amc->i2c_init = palmetto_bmc_i2c_init;
+ mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
mc->default_ram_size = 256 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1192,6 +1198,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 1;
amc->i2c_init = quanta_q71l_bmc_i2c_init;
+ mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
mc->default_ram_size = 128 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1211,6 +1218,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
+ mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
mc->default_ram_size = 256 * MiB;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/8] hw/arm/aspeed/2500: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2024-01-23 6:38 ` [PATCH 4/8] hw/arm/aspeed/2400: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 9:03 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 6/8] hw/arm/aspeed/2600: " Philippe Mathieu-Daudé
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index e0e0877b1d..df627096d2 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1152,6 +1152,11 @@ static const char * const ast2400_a1_valid_cpu_types[] = {
NULL
};
+static const char * const ast2500_a1_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("arm1176"),
+ NULL
+};
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1236,6 +1241,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = palmetto_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1253,6 +1259,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635f";
amc->num_cs = 1;
amc->i2c_init = ast2500_evb_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1271,6 +1278,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 2;
amc->i2c_init = yosemitev2_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1288,6 +1296,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = romulus_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1306,6 +1315,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx25l25635e";
amc->num_cs = 2;
amc->i2c_init = tiogapass_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1324,6 +1334,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = sonorapass_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1341,6 +1352,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
amc->spi_model = "mx66l1g45g";
amc->num_cs = 2;
amc->i2c_init = witherspoon_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1398,6 +1410,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = g220a_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 1024 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1416,6 +1429,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
amc->i2c_init = fp5280g2_bmc_i2c_init;
+ mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
mc->default_ram_size = 512 * MiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 6/8] hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2024-01-23 6:38 ` [PATCH 5/8] hw/arm/aspeed/2500: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 9:27 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 7/8] hw/arm/aspeed/1030: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 8/8] hw/arm/zynq: " Philippe Mathieu-Daudé
7 siblings, 1 reply; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index df627096d2..393c97d55e 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1157,6 +1157,11 @@ static const char * const ast2500_a1_valid_cpu_types[] = {
NULL
};
+static const char * const ast2600_a3_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+};
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1373,6 +1378,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
ASPEED_MAC3_ON;
amc->i2c_init = ast2600_evb_i2c_init;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1392,6 +1398,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1449,6 +1456,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = rainier_bmc_i2c_init;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1471,6 +1479,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
amc->macs_mask = ASPEED_MAC3_ON;
amc->i2c_init = fuji_bmc_i2c_init;
amc->uart_default = ASPEED_DEV_UART1;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = FUJI_BMC_RAM_SIZE;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1492,6 +1501,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON;
amc->i2c_init = bletchley_bmc_i2c_init;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1631,6 +1641,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
@@ -1651,6 +1662,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
amc->num_cs = 2;
amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
amc->i2c_init = qcom_dc_scm_firework_i2c_init;
+ mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
mc->default_ram_size = 1 * GiB;
mc->default_cpus = mc->min_cpus = mc->max_cpus =
aspeed_soc_num_cpus(amc->soc_name);
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 7/8] hw/arm/aspeed/1030: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2024-01-23 6:38 ` [PATCH 6/8] hw/arm/aspeed/2600: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 8/8] hw/arm/zynq: " Philippe Mathieu-Daudé
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/aspeed.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 393c97d55e..62d08899d8 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1162,6 +1162,11 @@ static const char * const ast2600_a3_valid_cpu_types[] = {
NULL
};
+static const char * const ast1030_a1_valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */
+ NULL
+};
+
static void aspeed_machine_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1613,6 +1618,7 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
+ mc->valid_cpu_types = ast1030_a1_valid_cpu_types;
amc->soc_name = "ast1030-a1";
amc->hw_strap1 = 0;
amc->hw_strap2 = 0;
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 8/8] hw/arm/zynq: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2024-01-23 6:38 ` [PATCH 7/8] hw/arm/aspeed/1030: " Philippe Mathieu-Daudé
@ 2024-01-23 6:38 ` Philippe Mathieu-Daudé
7 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 6:38 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, Cédric Le Goater, qemu-arm, Igor Mitsyanko,
Joel Stanley, Edgar E. Iglesias, Rob Herring,
Philippe Mathieu-Daudé
Restrict MachineClass::valid_cpu_types[] to the single
valid CPU type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
hw/arm/xilinx_zynq.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 66d0de139f..6ec65d4780 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -355,6 +355,10 @@ static void zynq_init(MachineState *machine)
static void zynq_machine_class_init(ObjectClass *oc, void *data)
{
+ static const char * const valid_cpu_types[] = {
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ NULL
+ };
MachineClass *mc = MACHINE_CLASS(oc);
mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
mc->init = zynq_init;
@@ -362,6 +366,7 @@ static void zynq_machine_class_init(ObjectClass *oc, void *data)
mc->no_sdcard = 1;
mc->ignore_memory_transaction_failures = true;
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
+ mc->valid_cpu_types = valid_cpu_types;
mc->default_ram_id = "zynq.ext_ram";
}
--
2.41.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 4/8] hw/arm/aspeed/2400: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 ` [PATCH 4/8] hw/arm/aspeed/2400: " Philippe Mathieu-Daudé
@ 2024-01-23 9:03 ` Cédric Le Goater
0 siblings, 0 replies; 13+ messages in thread
From: Cédric Le Goater @ 2024-01-23 9:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, qemu-arm, Igor Mitsyanko, Joel Stanley,
Edgar E. Iglesias, Rob Herring
On 1/23/24 07:38, Philippe Mathieu-Daudé wrote:
> Restrict MachineClass::valid_cpu_types[] to the single
> valid CPU type.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index cc59176563..e0e0877b1d 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1147,6 +1147,11 @@ static int aspeed_soc_num_cpus(const char *soc_name)
> return sc->num_cpus;
> }
>
> +static const char * const ast2400_a1_valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("arm926"),
> + NULL
> +};
> +
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -1175,6 +1180,7 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx25l25635f";
> amc->num_cs = 1;
> amc->i2c_init = palmetto_bmc_i2c_init;
> + mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
> mc->default_ram_size = 256 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1192,6 +1198,7 @@ static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx25l25635e";
> amc->num_cs = 1;
> amc->i2c_init = quanta_q71l_bmc_i2c_init;
> + mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
> mc->default_ram_size = 128 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1211,6 +1218,7 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
> amc->num_cs = 1;
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> + mc->valid_cpu_types = ast2400_a1_valid_cpu_types;
> mc->default_ram_size = 256 * MiB;
> }
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 5/8] hw/arm/aspeed/2500: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 ` [PATCH 5/8] hw/arm/aspeed/2500: " Philippe Mathieu-Daudé
@ 2024-01-23 9:03 ` Cédric Le Goater
0 siblings, 0 replies; 13+ messages in thread
From: Cédric Le Goater @ 2024-01-23 9:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, qemu-arm, Igor Mitsyanko, Joel Stanley,
Edgar E. Iglesias, Rob Herring
On 1/23/24 07:38, Philippe Mathieu-Daudé wrote:
> Restrict MachineClass::valid_cpu_types[] to the single
> valid CPU type.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> hw/arm/aspeed.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index e0e0877b1d..df627096d2 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1152,6 +1152,11 @@ static const char * const ast2400_a1_valid_cpu_types[] = {
> NULL
> };
>
> +static const char * const ast2500_a1_valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("arm1176"),
> + NULL
> +};
> +
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -1236,6 +1241,7 @@ static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc,
> amc->num_cs = 1;
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = palmetto_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1253,6 +1259,7 @@ static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx25l25635f";
> amc->num_cs = 1;
> amc->i2c_init = ast2500_evb_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1271,6 +1278,7 @@ static void aspeed_machine_yosemitev2_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx25l25635e";
> amc->num_cs = 2;
> amc->i2c_init = yosemitev2_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1288,6 +1296,7 @@ static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx66l1g45g";
> amc->num_cs = 2;
> amc->i2c_init = romulus_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1306,6 +1315,7 @@ static void aspeed_machine_tiogapass_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx25l25635e";
> amc->num_cs = 2;
> amc->i2c_init = tiogapass_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1324,6 +1334,7 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx66l1g45g";
> amc->num_cs = 2;
> amc->i2c_init = sonorapass_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1341,6 +1352,7 @@ static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
> amc->spi_model = "mx66l1g45g";
> amc->num_cs = 2;
> amc->i2c_init = witherspoon_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1398,6 +1410,7 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = g220a_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 1024 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1416,6 +1429,7 @@ static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
> amc->i2c_init = fp5280g2_bmc_i2c_init;
> + mc->valid_cpu_types = ast2500_a1_valid_cpu_types;
> mc->default_ram_size = 512 * MiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 6/8] hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()
2024-01-23 6:38 ` [PATCH 6/8] hw/arm/aspeed/2600: " Philippe Mathieu-Daudé
@ 2024-01-23 9:27 ` Cédric Le Goater
2024-01-23 9:35 ` Cédric Le Goater
0 siblings, 1 reply; 13+ messages in thread
From: Cédric Le Goater @ 2024-01-23 9:27 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, qemu-arm, Igor Mitsyanko, Joel Stanley,
Edgar E. Iglesias, Rob Herring
On 1/23/24 07:38, Philippe Mathieu-Daudé wrote:
> Restrict MachineClass::valid_cpu_types[] to the single
> valid CPU type.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
> hw/arm/aspeed.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index df627096d2..393c97d55e 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -1157,6 +1157,11 @@ static const char * const ast2500_a1_valid_cpu_types[] = {
> NULL
> };
>
> +static const char * const ast2600_a3_valid_cpu_types[] = {
> + ARM_CPU_TYPE_NAME("cortex-a9"),
This should be "cortex-a7"
Looking closer, the CPU information is under AspeedSoCClass. Why not build the
valid_cpu_types array with something like :
struct AspeedMachineClass {
...
const char *valid_cpu_types[2];
};
static void aspeed_machine_set_valid_cpu_types(MachineClass *mc)
{
AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
amc->valid_cpu_types[0] = sc->cpu_type;
amc->valid_cpu_types[1] = NULL;
mc->valid_cpu_types = amc->valid_cpu_types;
};
Thanks,
C.
> + NULL
> +};
> +
> static void aspeed_machine_class_init(ObjectClass *oc, void *data)
> {
> MachineClass *mc = MACHINE_CLASS(oc);
> @@ -1373,6 +1378,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
> ASPEED_MAC3_ON;
> amc->i2c_init = ast2600_evb_i2c_init;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1392,6 +1398,7 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1449,6 +1456,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = rainier_bmc_i2c_init;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1471,6 +1479,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
> amc->macs_mask = ASPEED_MAC3_ON;
> amc->i2c_init = fuji_bmc_i2c_init;
> amc->uart_default = ASPEED_DEV_UART1;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = FUJI_BMC_RAM_SIZE;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1492,6 +1501,7 @@ static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON;
> amc->i2c_init = bletchley_bmc_i2c_init;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1631,6 +1641,7 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
> @@ -1651,6 +1662,7 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
> amc->num_cs = 2;
> amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
> amc->i2c_init = qcom_dc_scm_firework_i2c_init;
> + mc->valid_cpu_types = ast2600_a3_valid_cpu_types;
> mc->default_ram_size = 1 * GiB;
> mc->default_cpus = mc->min_cpus = mc->max_cpus =
> aspeed_soc_num_cpus(amc->soc_name);
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 6/8] hw/arm/aspeed/2600: Check for CPU types in machine_run_board_init()
2024-01-23 9:27 ` Cédric Le Goater
@ 2024-01-23 9:35 ` Cédric Le Goater
0 siblings, 0 replies; 13+ messages in thread
From: Cédric Le Goater @ 2024-01-23 9:35 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Peter Maydell, Igor Mammedov, Alistair Francis, Gavin Shan,
Andrew Jeffery, qemu-arm, Igor Mitsyanko, Joel Stanley,
Edgar E. Iglesias, Rob Herring
On 1/23/24 10:27, Cédric Le Goater wrote:
> On 1/23/24 07:38, Philippe Mathieu-Daudé wrote:
>> Restrict MachineClass::valid_cpu_types[] to the single
>> valid CPU type.
>>
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
>> ---
>> hw/arm/aspeed.c | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
>> index df627096d2..393c97d55e 100644
>> --- a/hw/arm/aspeed.c
>> +++ b/hw/arm/aspeed.c
>> @@ -1157,6 +1157,11 @@ static const char * const ast2500_a1_valid_cpu_types[] = {
>> NULL
>> };
>> +static const char * const ast2600_a3_valid_cpu_types[] = {
>> + ARM_CPU_TYPE_NAME("cortex-a9"),
>
> This should be "cortex-a7"
>
> Looking closer, the CPU information is under AspeedSoCClass. Why not build the
> valid_cpu_types array with something like :
>
> struct AspeedMachineClass {
> ...
> const char *valid_cpu_types[2];
> };
>
> static void aspeed_machine_set_valid_cpu_types(MachineClass *mc)
> {
> AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(mc);
> AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name));
> amc->valid_cpu_types[0] = sc->cpu_type;
> amc->valid_cpu_types[1] = NULL;
> mc->valid_cpu_types = amc->valid_cpu_types;
> };
or better, change AspeedSoCClass::cpu_type to an array.
mc->valid_cpu_types =
ASPEED_SOC_CLASS(object_class_by_name(amc->soc_name))->cpu_types;
C.
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2024-01-23 9:36 UTC | newest]
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2024-01-23 6:38 [PATCH 0/8] hw/arm/cortex-a: Check for CPU types in machine_run_board_init() Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 1/8] hw/arm/exynos: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 2/8] hw/arm/highbank: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 3/8] hw/arm/vexpress: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 4/8] hw/arm/aspeed/2400: " Philippe Mathieu-Daudé
2024-01-23 9:03 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 5/8] hw/arm/aspeed/2500: " Philippe Mathieu-Daudé
2024-01-23 9:03 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 6/8] hw/arm/aspeed/2600: " Philippe Mathieu-Daudé
2024-01-23 9:27 ` Cédric Le Goater
2024-01-23 9:35 ` Cédric Le Goater
2024-01-23 6:38 ` [PATCH 7/8] hw/arm/aspeed/1030: " Philippe Mathieu-Daudé
2024-01-23 6:38 ` [PATCH 8/8] hw/arm/zynq: " Philippe Mathieu-Daudé
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