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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id mn6-20020a1709077b0600b00a2ccddf9a7dsm13874643ejc.124.2024.01.24.00.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 00:16:52 -0800 (PST) Date: Wed, 24 Jan 2024 09:16:51 +0100 From: Andrew Jones To: Akihiko Odaki Cc: Alex =?utf-8?Q?Benn=C3=A9e?= , qemu-devel@nongnu.org, Marcel Apfelbaum , "Edgar E. Iglesias" , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Michael Rolnik , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Laurent Vivier , kvm@vger.kernel.org, Yoshinori Sato , Pierrick Bouvier , Palmer Dabbelt , Liu Zhiwei , Laurent Vivier , Yanan Wang , qemu-ppc@nongnu.org, Weiwei Li , qemu-s390x@nongnu.org, =?utf-8?Q?C=C3=A9dric?= Le Goater , Peter Maydell , Alexandre Iooss , John Snow , Mahmoud Mandour , Wainer dos Santos Moschetta , Richard Henderson , Ilya Leoshkevich , Alistair Francis , David Woodhouse , Cleber Rosa , Beraldo Leal , Bin Meng , Nicholas Piggin , Aurelien Jarno , Daniel Henrique Barboza , Daniel Henrique Barboza , Thomas Huth , David Hildenbrand , qemu-riscv@nongnu.org, qemu-arm@nongnu.org, Paolo Bonzini , Song Gao , Eduardo Habkost , Brian Cain , Paul Durrant Subject: Re: Re: [PATCH v3 01/21] hw/riscv: Use misa_mxl instead of misa_mxl_max Message-ID: <20240124-3d9bec68bff7ab0057b902b6@orel> References: <20240122145610.413836-1-alex.bennee@linaro.org> <20240122145610.413836-2-alex.bennee@linaro.org> <20240123-b8d1c55688885bfc9125c42b@orel> <15d2f958-a51e-4b87-9a70-28edf3b55491@daynix.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <15d2f958-a51e-4b87-9a70-28edf3b55491@daynix.com> Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Wed, Jan 24, 2024 at 12:08:33PM +0900, Akihiko Odaki wrote: > On 2024/01/23 17:20, Andrew Jones wrote: > > On Mon, Jan 22, 2024 at 02:55:50PM +0000, Alex Bennée wrote: > > > From: Akihiko Odaki > > > > > > The effective MXL value matters when booting. > > > > I'd prefer this commit message get some elaboration. riscv_is_32bit() > > is used in a variety of contexts, some where it should be reporting > > the max misa.mxl. However, when used for booting an S-mode kernel it > > should indeed report the effective mxl. I think we're fine with the > > change, though, because at init and on reset the effective mxl is set > > to the max mxl, so, in those contexts, where riscv_is_32bit() should > > be reporting the max, it does. > > > > > > > > Signed-off-by: Akihiko Odaki > > > Message-Id: <20240103173349.398526-23-alex.bennee@linaro.org> > > > Message-Id: <20231213-riscv-v7-1-a760156a337f@daynix.com> > > > Signed-off-by: Alex Bennée > > > --- > > > hw/riscv/boot.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > > index 0ffca05189f..bc67c0bd189 100644 > > > --- a/hw/riscv/boot.c > > > +++ b/hw/riscv/boot.c > > > @@ -36,7 +36,7 @@ > > > bool riscv_is_32bit(RISCVHartArrayState *harts) > > > { > > > - return harts->harts[0].env.misa_mxl_max == MXL_RV32; > > > + return harts->harts[0].env.misa_mxl == MXL_RV32; > > > } > > > > Assuming everyone agrees with what I've written above, then maybe we > > should write something similar in a comment above this function. > > > > Thanks, > > drew > > The corresponding commit in my series has a more elaborated message: > https://patchew.org/QEMU/20240115-riscv-v9-0-ff171e1aedc8@daynix.com/20240115-riscv-v9-1-ff171e1aedc8@daynix.com/ I've pulled the message from that link and quoted it below > A later commit requires one extra step to retrieve misa_mxl_max. As > misa_mxl is semantically more correct and does not need such a extra > step, refer to misa_mxl instead. Below is the explanation why misa_mxl > is more semantically correct to refer to than misa_mxl_max in this case. > > Currently misa_mxl always equals to misa_mxl_max so it does not matter That's true, but I think that's due to a bug in write_misa(), which shouldn't be masking val with the extension mask until mxl has been extracted. > which of misa_mxl or misa_mxl_max to refer to. However, it is possible > to have different values for misa_mxl and misa_mxl_max if QEMU gains a > new feature to load a RV32 kernel on a RV64 system, for example. For > such a behavior, the real system will need the firmware to switch MXL to > RV32, and if QEMU implements the same behavior, mxl will represent the > MXL that corresponds to the kernel being loaded. Therefore, it is more > appropriate to refer to mxl instead of misa_mxl_max when > misa_mxl != misa_mxl_max. Right, but that doesn't say anything more than the original one line, "The effective MXL value matters when booting." What I'm looking for is a code comment explaining how riscv_is_32bit() is always safe to use. Something like /* * Checking the effective mxl is always correct, because the effective * mxl will be equal to the max mxl at initialization and also on reset, * which are the times when it should check the maximum mxl. Later, if * firmware writes misa with a smaller mxl, then that mxl should be * used in checks. */ Thanks, drew