From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: <qemu-devel@nongnu.org>, <linux-cxl@vger.kernel.org>,
Fan Ni <fan.ni@samsung.com>, Michael Tsirkin <mst@redhat.com>
Cc: "Davidlohr Bueso" <dave@stgolabs.net>,
linuxarm@huawei.com, "Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH 2/5] hw/cxl: Update link register definitions.
Date: Wed, 24 Jan 2024 13:48:11 +0000 [thread overview]
Message-ID: <20240124134814.8717-3-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20240124134814.8717-1-Jonathan.Cameron@huawei.com>
Not actually implemented, but we need to reserve more space for
the larger version of the structure in CXL r3.1.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
include/hw/cxl/cxl_component.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h
index 7d3edef1bf..2c7631bd1e 100644
--- a/include/hw/cxl/cxl_component.h
+++ b/include/hw/cxl/cxl_component.h
@@ -104,10 +104,10 @@ REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18)
(CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE)
#define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */
-/* 8.2.5.11 - CXL Link Capability Structure */
+/* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */
#define CXL_LINK_REGISTERS_OFFSET \
(CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE)
-#define CXL_LINK_REGISTERS_SIZE 0x38
+#define CXL_LINK_REGISTERS_SIZE 0x50
/* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */
#define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */
--
2.39.2
next prev parent reply other threads:[~2024-01-24 13:49 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-24 13:48 [PATCH 0/5 qemu] hw/cxl: Update CXL emulation to reflect and reference r3.1 Jonathan Cameron via
2024-01-24 13:48 ` [PATCH 1/5] hw/cxl: Update HDM Decoder capability to version 3 Jonathan Cameron via
2024-01-24 18:08 ` fan
2024-01-24 13:48 ` Jonathan Cameron via [this message]
2024-01-24 18:20 ` [PATCH 2/5] hw/cxl: Update link register definitions fan
2024-01-24 13:48 ` [PATCH 3/5] hw/cxl: Update RAS Capability Definitions for version 3 Jonathan Cameron via
2024-01-24 18:26 ` fan
2024-01-24 13:48 ` [PATCH 4/5] hw/cxl: Update mailbox status registers Jonathan Cameron via
2024-01-24 18:57 ` fan
2024-01-24 13:48 ` [PATCH 5/5] hw/cxl: Standardize all references on CXL r3.1 and minor updates Jonathan Cameron via
2024-01-24 20:58 ` fan
2024-01-26 11:43 ` Jonathan Cameron via
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