From: Andrew Jones <ajones@ventanamicro.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org,
alistair.francis@wdc.com, bmeng@tinylab.org,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
palmer@rivosinc.com
Subject: Re: [PATCH 6/6] target/riscv: Promote svade to a normal extension
Date: Fri, 26 Jan 2024 14:03:27 +0100 [thread overview]
Message-ID: <20240126-a0cd03d186454ff0a98f7911@orel> (raw)
In-Reply-To: <20240125195319.329181-7-dbarboza@ventanamicro.com>
On Thu, Jan 25, 2024 at 04:53:19PM -0300, Daniel Henrique Barboza wrote:
> From: Andrew Jones <ajones@ventanamicro.com>
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense for users to control, so treat
> it like a "normal" extension. The default is false, since QEMU has
> always implemented hardware A/D PTE bit updating, so users must opt into
> svade (or get it from a CPU type which enables it by default).
>
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
> target/riscv/cpu.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a56c2ff91d..4ddde25412 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -1421,6 +1421,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
>
> MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
> MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
> + MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
I forgot that the 'max' cpu type will ignore this off by default setting
and enable svade by default. I'll send a v2 of this series where I ensure
svade for 'max' also defaults false.
Thanks,
drew
> MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
> MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
> MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
> @@ -1528,7 +1529,6 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
> * and priv_ver like regular extensions.
> */
> const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
> - MULTI_EXT_CFG_BOOL("svade", ext_svade, true),
> MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
>
> /*
> @@ -2175,8 +2175,6 @@ static RISCVCPUProfile RVA22U64 = {
> * Other named features that we already implement: Sstvecd, Sstvala,
> * Sscounterenw
> *
> - * Named features that we need to enable: svade
> - *
> * The remaining features/extensions comes from RVA22U64.
> */
> static RISCVCPUProfile RVA22S64 = {
> @@ -2188,11 +2186,11 @@ static RISCVCPUProfile RVA22S64 = {
> .ext_offsets = {
> /* rva22s64 exts */
> CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
> - CPU_CFG_OFFSET(ext_svinval),
> + CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
>
> /* rva22s64 named features */
> CPU_CFG_OFFSET(ext_sstvecd), CPU_CFG_OFFSET(ext_sstvala),
> - CPU_CFG_OFFSET(ext_sscounterenw), CPU_CFG_OFFSET(ext_svade),
> + CPU_CFG_OFFSET(ext_sscounterenw),
>
> RISCV_PROFILE_EXT_LIST_END
> }
> --
> 2.43.0
>
prev parent reply other threads:[~2024-01-26 13:04 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-25 19:53 [PATCH 0/6] riscv: named features riscv,isa, 'svade' rework Daniel Henrique Barboza
2024-01-25 19:53 ` [PATCH 1/6] target/riscv/tcg: set 'mmu' with 'satp' in cpu_set_profile() Daniel Henrique Barboza
2024-01-30 0:57 ` Alistair Francis
2024-01-25 19:53 ` [PATCH 2/6] target/riscv: add riscv,isa to named features Daniel Henrique Barboza
2024-01-30 1:07 ` Alistair Francis
2024-01-25 19:53 ` [PATCH 3/6] target/riscv: add remaining " Daniel Henrique Barboza
2024-01-30 1:10 ` Alistair Francis
2024-01-31 19:15 ` Daniel Henrique Barboza
2024-02-02 2:14 ` Alistair Francis
2024-02-02 9:44 ` Daniel Henrique Barboza
2024-02-05 6:16 ` Alistair Francis
2024-01-25 19:53 ` [PATCH 4/6] target/riscv: Reset henvcfg to zero Daniel Henrique Barboza
2024-01-25 19:53 ` [PATCH 5/6] target/riscv: Gate hardware A/D PTE bit updating Daniel Henrique Barboza
2024-01-25 19:53 ` [PATCH 6/6] target/riscv: Promote svade to a normal extension Daniel Henrique Barboza
2024-01-26 13:03 ` Andrew Jones [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20240126-a0cd03d186454ff0a98f7911@orel \
--to=ajones@ventanamicro.com \
--cc=alistair.francis@wdc.com \
--cc=bmeng@tinylab.org \
--cc=dbarboza@ventanamicro.com \
--cc=liwei1518@gmail.com \
--cc=palmer@rivosinc.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).